Sanjay Banerjee

Cockrell Family Regents Chair in Engineering

Professor, Electrical and Computer Engineering, University of Texas at Austin

http://www.ece.utexas.edu/people/faculty/sanjay-banerjee

Dr. Sanjay Banerjee is the Cockrell Family Regents Chair Professor of Electrical and Computer Engineering and the Director of the Microelectronics Research Center in the Department of Electrical & Computer Engineering at The University of Texas at Austin. He received his B.Tech from the Indian Institute of Technology, Kharagpur, and his M.S. and Ph.D. from the University of Illinois at Urbana-Champaign in 1979, 1981 and 1983 respectively, all in electrical engineering. As a Member of the Technical Staff, Corporate Research, Development and Engineering of Texas Instruments Incorporated from 1983-1987, he worked on polysilicon transistors and dynamic random access trench memory cells used by Texas Instruments in the world's first 4Megabit DRAM, for which he was co-recipient of the Best Paper Award, IEEE International Solid State Circuits Conference, 1986.

Novel Low Power Transistors in 2D Dirac Materials: Graphene and Topological Insulators

The semiconductor industry is placing increasing emphasis on emerging materials and devices that may provide solutions to end-of-the-CMOS-roadmap problems beyond 2020.  The remarkable electronic properties of graphene and topological insulators can lead to novel beyond-CMOS logic and memory device concepts. One such concept, the Bilayer pseudoSpin FET (BiSFET), could potentially be an ultra-low power replacement for the MOSFET. The BiSFET is based on many-body tunneling of an excitonic Bose condensate in double layer graphene. One can also have single particle 2D-to-2D tunneling FETs based on the BiSFET architecture, with similar current-voltage behavior demonstrating negative differential resistance.

Graphene has a single-atom thickness, zero bandgap, symmetric conduction and valence band structure around the Dirac point, and low band edge density of states, which combined makes it theoretically attractive for the formation of an excitonic condensate.  SPICE simulations demonstrate that fundamental Boolean gates such as inverters, OR and NAND gates can be implemented with the BiSFET, using a 4-phase clocked power supply, with much lower power dissipation and comparable or faster switching than CMOS. In addition, more complicated circuits such as 4-bit adders, as well as simple memory elements, can be achieved leading to the possibility of both sequential and combinatorial logic. Experimentally, the BiSFET has not been demonstrated so far.  Thinner (~1nm) interlayer and lower-k dielectrics than currently used appear to be required and are now being explored.   

The basic BiSFET device structure could also be used as 2D-2D single particle tunnel FETs. For the single particle h-h and e-e 2D-2D tunnel FETs, graphene’s single-atom thickness could lead to more ideal interlayer tunneling characteristics, provided the layers can be aligned.  Single particle tunneling current calculations have been performed which show NDR characteristics, reminiscent of the BiSFET, albeit with higher operating powers.

Finally, the spin-helically locked Dirac cone surface states in a topological insulator can be the basis of new types of non-volatile memory and logic. Several such ideas will be briefly discussed.

Phil Emma

Chief Scientist, IBM Research
IBM Thomas J. Watson Research Center, NY

Dr. Phil Emma, Chief Scientist at IBM Research, got his PhD in Electrical Engineering from the University of Illinois a while ago, and joined the IBM Watson Research Laboratory to work for von Neumann’s Chief Engineer. He has worked in the areas of microarchitecture, architecture, systems design, circuit design, electronic packaging, interconnection technology, and optics. He has also served as an adjunct professor at several universities. He has written well over 100 technical articles and several book chapters, and holds over 150 patents. He has worked as a Design Lead in Development, and led the Systems Technology and Microarchitecture group at IBM Watson, which works on exploring and leveraging new physical technologies within the context of systems design. He has spent the last few years looking at opportunities for 3D in Architecture. He is a member of the IBM Academy of Technology, and a Fellow of the IEEE.

Some Future Dimensions in Scaling

As we all know, we are (again) approaching the end of CMOS scaling, but this time it’s true. As (primarily) an Architect, I think that what the CMOS roadmap did for us was to make substantial innovation unnecessary. At a high level, the computers that we make today are (operationally) the same as the one that von Neumann made ages ago, albeit with some whistles and bells. I think that today, we have an opportunity and a motivation to take what we call “computing” into some new dimensions using new technology innovation, some new circuits, and some new concepts of “state.” While there are many directions, I will discuss (primarily) 3D technology, and touch on a few more, with the caveat that today, lots of this will be consumer-driven.

Variability-Resistant HW/SW Stack Through Improved Sensing

Variability in delivered performance by sensing and computing devices is a growing reliability challenge. Manufacturing variability has traditionally been handled through overdesign by hardware system designers. Unfortunately, the overdesign margins have become prohibitively expensive and infeasible with the growing scale of designs. In an alternate universe, sensing of the physical environment could provide important data to adjust software/computation at different levels. In this talk, I will discuss our experiments to characterize variability, program structuring and task scheduling that make a software stack robust against variations in the computing environment.

 

This talk represents part of the effort at NSF Expeditions in Computing program on Variability.

Dr. Ian A. Young

Senior Fellow and Director of Exploratory Integrated Circuits, Components Research
Intel Corporation, Hillsboro, Oregon
 

Ian Young is a Senior Fellow and director of Exploratory Integrated Circuits in the Technology and Manufacturing Group of Intel Corporation.  He joined Intel in 1983 and his technical contributions have been in the design of DRAMs, SRAMs, microprocessor circuit design, Phase Locked Loops and microprocessor clocking, mixed-signal circuits for microprocessor high speed I/O links, RF CMOS circuits for wireless transceivers, and research for chip to chip optical I/O.  He has also contributed to the definition and development of Intel’s process technologies. He now leads a research group exploring the future options for the integrated circuit in the beyond CMOS era. Recent work has developed a uniform benchmarking to identify the technology options in spintronics, tunneling junction field-effect and photonics devices.

Ian Young received the Bachelor of Electrical Engineering and the Master Eng. Science, Microwave Communications, from the University of Melbourne, Australia. He received the PhD in Electrical Engineering from the University of California, Berkeley. He is the recipient of the 2009 International Solid-State Circuits Conference's Jack Raper Award for Outstanding Technology Directions paper. He is a Fellow of the IEEE.

Exploring the Beyond CMOS Options for Energy Efficient Computation

CMOS integrated circuit technology for computation is at an inflexion point. Although this is the technology which has enabled the semiconductor industry to make vast progress over the past 30-plus years, it is expected to see challenges going beyond the ten year horizon, particularly from an energy efficiency point of view.  Thus it is extremely important for the semiconductor industry to discover a new integrated circuit technology which can carry us to the beyond CMOS era, so that the power-performance of computing can continue to improve.  Currently, researchers are exploring novel device concepts and new information tokens as an alternative for CMOS technology.  Examples of areas being actively researched are; quantum electronic devices, such as the tunneling field-effect transistor (TFET), devices based on electron spin and nano-magnetics (spintronics), and synchronization of coupled- oscillator arrays for non-boolean logic associated memory. It is clear that choices will need to be made in the next few years to identify viable alternatives for CMOS by 2020.  To prioritize and guide the research exploration, benchmarking methodology and metrics are being used.

This talk will give an overview of the beyond CMOS device research horizon and the benchmarking of these devices for computation.  A more detailed investigation of circuits based upon some promising beyond-CMOS devices will follow. First the differences of TFET circuits from CMOS will be described together with their potential for significant improvement in computational energy efficiency.  Next spintronic devices will be discussed. These are potential candidates to complement CMOS technology due to the promise of non-volatility and compact implementation of logic function. One promising device, called the All-Spin Logic (ASL) device will be explained.  A complete static ASL logic family comprised of majority logic gates, operating from 10mV power supplies, has been functionally validated with physics-based models and a spin circuit theory based circuit simulator. Along with the implementations of sequencing elements (e.g., latch and D flip-flop), clocked ASL can implement all the functional blocks for general purpose computation. The last topic introduces a novel concept to improve computational energy efficiency for pattern recognition. It will describe a non-boolean logic associative memory based upon arrays of synchronizing coupled oscillators.