Technical Program

Updated July 6th 2015
Available Here
Thank You

for a Wonderful ISVLSI 2015
Check out the Photo Gallery and Closing Remarks
Photo Gallery|Closing Remarks

Experience Montpellier

In The South of France

About the Venue

ISVLSI 2015

08–10July2015Montpellier, France

Call for Papers

About

ISVLSI 2015

08 - 10 July 2015, Montpellier. France

Featuring contributions focused on the emerging trends and novel ideas and concepts in the area of VLSI.

The Vision

This Symposium explores emerging trends, novel ideas and concepts in the area of VLSI. The Symposium covers a range of topics: from VLSI circuits, systems and design methods to system level design and system-on-chip issues, to bringing VLSI experience to new areas and technologies like nano- and molecular devices, MEMS, and quantum computing. Future design methodologies will also be one of the key topics at the workshop, as well as new CAD tools to support them. Over almost two decades the symposium has been an unique forum promoting multidisciplinary research and new visionary approaches in the area of VLSI. The Symposium is bringing together leading scientists and researchers from academia and industry. The papers from this symposium have been published as the special issues of top archival journals. This fact indicates a very high quality of the sympo-sium papers, and we are determined to keep a strong emphasis on this critical aspect of any conference. The symposium proceedings are published by IEEE Computer Society Press. The Symposium has established a reputation in bringing well-known international scientists as invited speakers, and this trend will continue.

Seeking

Contributrions are sought in the following areas: Emerging Trends in VLSI, Nanoelectronics, Molecular, Biological and Quantum Computing. MEMS, VLSI Circuits and Systems, Field-programmable and Reconfigurable Systems, System Level Design, System-on-a-Chip Design, Application-Specific Low Power, VLSI System Design, System Issues in Complexity, Low Power, Heat Dissipation, Power Awareness in VLSI Design, Test and Verification, Mixed-Signal Design and Analysis, Electrical/Packaging Co-Design, Physical Design, Intellectual property creating and sharing.

Details

The Symposium Program will include contributed papers and speakers invited by the Program Committee, as well as a poster session. The keynote addresses, panels and special sessions are planned as well. Authors should submit their original work using the web based submission system. Initial submissions to the conference are limited to six pages. ISVLSI uses double blind review mechanism and authors information should not be provided in the initial manuscript. All submissions should be in PDF format.

Early Registration Countdown

Author Information and News

May 2015

Technical Program

We are pleased to announce the technical program for ISVLSI 2105 - available here as a pdf).

February 2015
Student Travel Grants and Awards:
We are pleased to announce Student Funding Grants for travel to and best paper at ISVLSI 2015 sponsored by The Technical Committee on VLSI of the IEEE Computer Society (TCVLSI):
- TCVLSI Student Travel ( 4 grants) - $250 each
- TCVLSI Student Best Paper Award (1) - $100
September 2014
Call for Papers
The Symposium Program will include contributed papers and speakers invited by the Program Committee, as well as a poster session.

Submission Guidelines:
Submitted papers should be a maximum of 6 pages using the IEEE-CS conference format - template available here.
Important Dates:
- Paper Submission Deadline:
  EXTENDED: March 9, 2015
- Acceptance Notification:
  April 20, 2015
- Submission of Final Version:
  May 13, 2015
Tracks
- Digital Circuits and FPGA based Designs (DCF): Digital circuits, chaos/neural/fuzzy-logic circuits, high-speed/low-power circuits, energy efficient circuits, near and sub-threshold circuits, memories, FPGA designs, FPGA based systems.
- Computer-Aided Design and Verification (CAD): Hardware/software co-design, logic and behavioral synthesis, simulation and formal verification, physical design, signal integrity, power and thermal analysis, statistical approaches.
- Emerging and Post-CMOS Technologies (EPT): Nanotechnology, molecular electronics, quantum devices, optical computing, spin-based computing, biologically-inspired computing, CNT, SET, RTD, QCA, reversible logic, and CAD tools for emerging technology devices and circuits.
- System Design and Security (SDS): Structured and Custom Design methodologies, microprocessors/micro-architectures for performance and low power, embedded processors, analog/digital/mixed-signal systems, NoC, power and temperature aware designs, Hardware security, Cryptography, watermarking, and IP protection, TRNG and security oriented circuits, PUF circuits.
- Testing, Reliability, and Fault-Tolerance (TRF): Digital testing, design for testability and reliability, online testing techniques, static and dynamic defect- and fault-recoverability, and variation-aware design.
- Analog and Mixed-Signal Circuits (AMS): Analog/mixed-signal/RF circuit design and testing, RF and communication circuits, adaptive circuits, interconnects, VLSI aspects of sensor and sensor network.
Details... | Submit your paper manuscript now
September 2014
Special Sessions Call:
The ISVLSI 2015 technical program will include Special Sessions. These sessions are meant to complement the regular sessions by giving a broad overview on a new and emerging topic of interest to the ISVLSI community.
Important Dates:
- Special Session Proposals Due:
  January 20, 2015
- Notification of Accepted Proposals:
  February 20, 2015
- Submission for Special Session Papers:
  Extended - April 30, 2015
Details... | Submit your special session proposal now

Request

for Special Sessions!
Due: January 20, 2015

The ISVLSI 2015 technical program will include Special Sessions. These sessions are meant to complement the regular sessions by giving a broad overview on a new and emerging topic of interest to the ISVLSI community.
Read the full Special Session Call here
Important Dates:
- Special Session Proposals Due:
  January 20, 2015
- Notification of Accepted Proposals:
  February 20, 2015
- Submission for Special Session Papers:
  Extended - April 20, 2015
Submit you proposal now

PhD Forum

ISVLSI 2015 Ph.D Forum

Supported by the
ISVLSI 2015 will host a Ph.D. forum, providing opportunity for Ph.D. students to present their thesis work to a broad audience in the VLSI community from both industry and academia. The Ph.D. forum may also help students to establish contacts for entering the job market. On the other side, representatives from industry and academia get a glance of state-of-the-art in system design and design automation.

Eligibility
Students who have finished their Ph.D. dissertation/thesis within the last 12 months or students who will finish to their thesis work in less than one year.

Selection
Approximately 10 students will be selected for oral presentation at ISVLSI 2015 and will also have their papers included in the proceedings.
Benefit to selected students
- 4-page publication in the ISVLSI 2015 proceedings (indexed in IEEE eXplore).
- Presentation in poster session for Ph.D. Forum.
- Networking with presenters from industry and academia.
- 50% discount on the registration fee and a free dinner registration.
- Opportunity to publicize work, distribute flyers summarizing PhD work.
- Best PhD poster award will be presented during conference banquet. Award based on presentation and poster quality.
- Cadence will support the best PhD Forum paper
Author Information
- Please submit a paper in IEEE conference format describing problem addressed in the thesis, novelty of the solution, observations and analysis. Focus should be on the scientific challenges and solutions. IEEE template can be found here.
- Page limit: 4. Please do not exceed the page limit.
- The submission should not include author information to enable blind review.
- A single pdf file should be submitted here
  and selecting the "Ph.D Forum" track during submission.
Important Dates
- Paper Submission Deadline: EXTENDED: March 14th, 2015
- Acceptance Notification: April 15th, 2015
- Submission of Final Version: April 30th, 2015
For inquiry please contact: The "Ph.D. Forum Chair" Michael HÃ¼bner and Patrick Haspel from the Organizing Committee list.

Venue

The Symposium Will Be Held At

Faculte de Medecine

The venue's address is:
FacultÃ© de MÃ©decine de Montpellier
2 Rue de l'Ecole de Medecine
34000 Montpellier
France

Getting Here

By plane, you can either use the Lyon / Paris hub (flight from Lyon or Paris to Montpellier takes around 1h) or use the low cost companies in and around Montpellier. Check RyanAir and EasyJet for further details. Please note that around Montpellier there will be several airports such as Beziers, Avignon or Carcassonne opened during the summer. Marseille or Lyon are at around 2h by train from Montpellier.

Please note that there are several international destinations accessible on direct trains (Valencia, Barcelona, Bruxelles). To book your train ticket you can use the Voyages SNCF website. The sooner you book your ticket the cheaper it is. Since Montpellier is a very popular touristic destination during the summer, we advise booking in advance.

By Air

The Montpellier Mediterranean International Airport (MPL) is located 10 km from downtown.

15 daily flights between Montpellier and Paris Orly (ORY) and Roissy-Charles-De-Gaulle (CDG) airports (flight time only 1h10)
3 daily flights between Montpellier and Lyon
57 international destinations, served by 11 traditional and low-cost airlines (AirArabia, AirFrance, AirMÃ©diterranÃ©e, EasyJet, Fram, Iberia, RyanAir)

Getting To Town

When arriving at the airport there are two possibilities. Either take a shuttle bus in front of the terminal, or take a taxi.

There is an airport shuttle with convenient departures after every flight from Paris. Arrival at â€œPlace de lâ€™Europeâ€ in the Antigone district of Montpellier. It takes 15-20 minutes to get to the town center. Tickets are on sale at the bus shuttle. Single fare ticket (for the bus shuttle only) 1,60â‚¬ (one-way)
Intermodal ticket with city bus/TaM included. Arrival at âPlace de l'Europeâ€ and then take the tramway: Line 1 â Direction Mosson and Stop at â Place De la Comediee, 2,60â‚¬ (one-way)
Please note that the taxi to the city center is around 30 euros (depending on the time and the number of luggage you have). The best is to share a taxi with people going to the city center and then take the tram to your hotel location. The trams run until 1AM and tickets can be purchased in every tram station.

By Train

The SNCF train station is located in the town center, with several high speed trains (TGV) to and from Paris every day. The trip to Paris takes around 3h30. The two major cities, Lyon and Marseille (which both have an international airport), are both within 2h by train, and Barcelona (Spain) at about 4h30.

The Station in Montpellier is 5 minutes away from Â«Le Faculte de MedecineÂ»
The High Speed Train connects to: Paris (Roissy-CDG Airport) (11 trains/day) - 3h30m, Lyon, and Lille.
The High Speed Train also has International connections to Barcelona, Brussels and Geneva

Hotels / Accommodations

Please visit this external site to book your accomodations!

Keynote Speakers

Heike Riel

IBM Research – Zurich

The Future of Nanoelectronics: New Materials, Architectures and Devices

Technological breakthroughs have led to enormous improvements in performance, power, functionality and cost of computing devices and have thus enabled 50 years of Moore’s law. Cost per function has decreased several thousand fold, while system performance and reliability have been improved dramatically. Today conventional silicon transistor scaling is approaching fundamental physical limits. For example, the increasing power dissipation on the chip level is one of the key challenges. Rising leakage currents and the increasing difficulty to further reduce the supply voltage have impacted the passive and active power dissipation, limiting the overall performance. Therefore a key attribute of any new device that may be considered for replacing the conventional field-effect transistor (FET) is reduced power dissipation. In that respect new strategies, including the use of novel materials, innovative device architectures and device concepts need to be explored and assessed.
Attention has turned to III–V compound semiconductors that are well positioned to replace silicon as the base material in logic switching devices. Their outstanding electron transport properties and the possibility to tune heterostructures provide tremendous opportunities to engineer novel nanometerscale logic transistors. The scaling constraints require an evolution from planar III–V metal oxide semiconductor field-effect transistors (MOSFETs) toward transistor channels with a three-dimensional structure, such as nanowire FETs, to achieve future performance needs for complementary metal oxide semiconductor (CMOS) nodes beyond 10 nm.
Carbon nanotubes (CNT) represent another class of semiconductor materials possessing transport properties more attractive than silicon to lower operation voltage and thus power consumption of MOSFETs. The superior low-voltage performance of sub-10 nm CNT transistors proves the viability of nanotubes for consideration in future aggressively scaled transistor technologies. Still challenges such as precise positioning and low contact resistance remain for large-scale integration.
Further device innovations are required to increase energy efficiency. This could be addressed by devices with a steeper subthreshold slope compared to MOSFETs to enable scalingof voltage supply and future low-power designs. In that regard, tunnel FETs (TFETs) are very promising as they allow to achieve a subthreshold swing of below 60 mV/dec. at room temperature by utilizing band-to-band-tunneling (BTBT) for charge injection. To achieve the required TFET performance boosters such as heterostructures are needed to lower the effective tunnel barrier and enable steep slope and high on-currents.
This presentation describes the challenges and recent progress toward the most prominent candidates for becoming the next nanoelectronic switch where new materials, architectures and devices are crucial.
Tanya Nigam and Andreas Kerber

GLOBALFOUNDRIES

Enabling scaling of advanced CMOS technologies: A reliability perspective

PAs CMOS technologies continue to scale and devices become more interconnected, new reliability challenges are emerging. With Internet-of-Things, semiconductor devices will be ubiquitous and used under diverse environmental conditions. In this paper we will review the device level scaling challenges from the reliability perspective, which include new materials, variability in ever decreasing dimensions, and methodology enhancements needed to provide reliable solutions across different product segments. The critical need for product level reliability assessment will be highlighted to provide additional margin for the consumer market.
As we move towards the sub 20 nm regime, a convergence of application is occurring in the product segment. As shown in Fig. 1, a typical product like a cell phone currently provides not only enhanced computing power (CPU and GPU) but also encompass many sensors such as accelerometers, gyroscopes, and microphone. As we move towards IoT, connecting devices and ensuring a secure and reliable data collection/transfer will be critical. All of this must come at a reduced cost and shorter development times. The trade-off between power and performance becomes more demanding as well. Reliability of individual components may need a re-evaluation and assessing over all product reliability where failure of any one of the diverse components leads to product failure needs to be addressed.
The power performance trade off in device scaling, has been addressed via material changes and device architecture change. Material changes include introduction of Hf-based HK dielectric stacks to replace SiON gate dielectric. Ultra Low K dielectrics for Back end of Line dielectrics and material/interface optimization for EM. For sub 10nm technologies new channel materials such III-V and SiGe are being explored along with FINFET and Gate all around Nanowire. Each of these approaches brings new challenges and solutions to technology scaling. A third component of scaling is managing variability both at Time zero and those induced due to defect generation under operating conditions. Understanding and modeling these variability components is also critical for future nodes. Finally, it is critical to correlate the device level learning to product operation. Starting block for such studies can be ring oscillators for logic and small array of SRAM for memory. Implication of device degradation over time on Logic and SRAM Vmin needs to be understood and appropriate guard band is needed during technology definition.
In this presentation, we summarize reliability challenges due to material change in current and future technology nodes. We will provide an overview of key physical mechanisms which are impacted due to change in gate dielectric stack from SiON to HK MG. A short overview of the changes in BEOL material and its impact on electro-migration and ILD TDDB will be discussed. Move to FINFETs with III-V channel material will be briefly touched. Impact of variability both time zero and post stress will be elaborated. Current and future approaches to bridge the gap between Wafer Level Reliability and product level reliability challenges will be highlighted.

Sponsorship plays a major role in the success of ISVLSI

Find out more about each of our sponsors by clicking on the logos below.

Organizing Committee

General Chairs
- Aida Todri-Sanial, CNRS-LIRMM, France
- Giorgio Di Natale, CNRS-LIRMM, France
- Patrick Girard, CNRS-LIRMM, France
Program Chairs
- Marc Belleville, CEA-LETI, France
- Saraju Mohanty, University of North Texas, USA
Publication Chairs
- Mariane Comte, University of Montpellier 2, France
- Lu Peng, Louisiana State University, USA
Financial Chair
- Abdoulaye Gamatie, CNRS-LIRMM, France
Local Arrangement Chair
- Nadine Azemard-Crestani, CNRS LIRMM, France
Special Session Chairs
- Monica Pereira, UFRN, Brazil
- Xin Li, Carnegie Mellon University, USA
Web Chairs
- Theocharis Theocharides, University of Cyprus, Cyprus
- Mike Borowczak, Erebus Labs, USA
Registration Chair
- Vincent Kerzerho, CNRS-LIRMM, France
Industrial Liaison Chair
- Lionel Torres, University of Montpellier 2, France
Ph.D. Forum Co-Chairs
- Michael HÃ¼bner, Ruhr University Bochum, Germany
- Patrick Haspel, Strategic Academic Partnerships, Cadence Design Systems
Publicity Chairs
- Vasilis Pavlidis, University of Manchester, UK
- Prasun Ghosal, Indian Institute of Engineering Science and Technology, Shibpur, India
- Annajirao Garimella, Intel Corporation
- Nikolaos Voros, Technological Educational Institute of Western Greece
International Liaison Chairs
- Brazil: Ricardo Reis, Federal University of Rio Grande do Sul (UFRGS), Brazil
- China/South-East Asia: Jiang Xu, Hong Kong University of Science and Technology, China
- Germany: Jurgen Becker, Karlsruhe Institute of Technology, Germany
- Greece: Nicolas Sklavos, University of Patras, Greece
- India: Susmita Sur-Kolay, Indian Statistical Institute, Kolkata, India
Steering Committee Chair
- Nagarajan Ranganathan, University of South Florida, USA
Technical Program Committee

Analog and Mixed-Signal Circuits (AMS)

Chairs
- Ashok Srivastava, Louisiana State University
- Florence Azais, LIRMM
Members
- Amir Zjajo, Delft University of Technology
- Changzhi Li, Texas Tech University
- Dhruva Ghai, Oriental University
- Gildas Leger, Instituto de Microelectronica de Sevilla (IMSE-CNM-CSIC)
- JosÃ© Machado Da Silva, FEUP
- Manisha Goswami, Indian Institute of Information Technology Allahabad
- Manisha Pattanaik, IIIT Gwalior
- Maryam Baghini, Indian Institute of Technology Bombay
- Steffen Paul, University of Bremen
- Vincent Kerzerho, LIRMM, CNRS/Univ. Montpellier 2
- Xin Li, Carnegie Mellon University
Computer Aided Design and Verification (CAD)

Chairs
- Massimo Poncino, Polytechnic University of Turin
- Mircea Stan, University of Virginia
Members
- Aida Todri-Sanial, CNRS-LIRMM
- Ke Wang, University of Virginia
- Kunal Ganeshpure, Mentor Graphics Corporation
- Michael Huebner, Ruhr-University Bochum
- Nagi Naganathan, Avago
- Shih-Hsu Huang, Chung Yuan Christian University
- Theocharis Theocharides, University of Cyprus
- Yann Thoma, HEIG-VD
Digital Circuits and FPGA based Designs (DCF)

Chairs
- Jia Di, University of Arkansas
- Elaheh (Eli) Bozorgzadeh, University of California Irvine
Members
- Bharat Joshi, University of North Carolina at Charlotte
- Christophe Jego, IMS Laboratory
- Christophe Bobda, University of Arkansas
- David Bol, UniversitÃ© catholique de Louvain
- Dimitrios Soudris, NTUA
- Dr. Anirban Sengupta, Indian Institute of Technology (IIT) Indore
- Hailong Jiao, Eindhoven University of Technology
- Hao Zheng, Univ of South Florida
- Ning Weng, Southern Illinois University Carbondale
- Ron Demara, University of Central Florida
- Shanq-Jang Ruan Ruan, National Taiwan University of Science and Technology
- Srinidhi Kestur, Broadcom corporation
- Xuelian Liu, Rensselaer Polytechnic Institute
Emerging and post-CMOS Technologies (EPT)

Chairs
- Sanjukta Bhanja, University of South Florida
- Ian O'Connor, University of Lyon
Members
- Arthur Nieuwoudt, Synopsys
- Hai Li, University of Pittsburgh
- Himanshu Thapliyal, Qualcomm Technologies, Inc.
- Jiang Xu, Hong Kong Universtiy of Science and Technology
- Kumar Yelamarthi, Central Michigan University
- Lionel Torres, LIRMM
- Prasun Ghosal, Indian Institute of Engineering Science and Technology, Shibpur
- Rashmi Jha, University of Toledo
- Saraju Mohanty, University of North Texas
- Thomas Mikolajick, TU Dresden, Chair of Nanoelectronic Materials University of Technology Dresden, Faculty of Electrical and Computer Engineering
System Design and Security (SDS)

Chairs
- Garrett Rose, University of Tennessee
- Ricardo Chaves, IST TULisbon/INESC-ID
Members
- Apostolos Fournaris, University of Patras
- Chengmo Yang, University of Delaware
- David Hely, Grenoble INP
- Guy Gogniat, UniversitÃ© de Bretagne Sud - UEB
- Jude Ambrose, University of New South Wales
- Luciano Ost, University of Leicester
- Madhu Mutyam, Indian Institute of Technology, Madras.
- Mateus Rutzig, Federal University of Santa Maria
- Mehran Kermani, Rochester Institute of Technology
- Michail Maniatakos, New York University Abu Dhabi
- Naghmeh Karimi, New York University
- Nele Mentens, KU Leuven
- Philippe Maurine, CEA
- Rance Rodrigues, University of Massachusetts at Amherst
- Tanguy Risset, Citi, INSA-Lyon
- Yier Jin, The University of Central Florida
Testing, Reliability, Fault-Tolerance (TRF)

Chairs
- Alberto Bosio, LIRMM
- Lorena Anghel, TIMA
Members
- Dong Xiang, Tsinghua University
- Irith Pomeranz, Purdue University
- Katherine-Shu-Min Li, National Sun Yat-sen University
- Leticia-Maria Bolzani-Poehls, PUCRS
- Matteo Sonza Reorda, Politecnico di Torino
- Michel Renovell, LIRMM
- Michele Portolan, TIMA
- Mihalis Psarakis, University of Piraeus
- Paolo Bernardi, Politecnico di Torino
- Vishwani Agrawal, Auburn University
- Xiaoqing Wen, Kyushu Institute of Technology
- Zebo Peng, Linkping University

Technical Program

Updated July 6th 2015

Thank You

for a Wonderful ISVLSI 2015 Check out the Photo Gallery and Closing Remarks

Experience Montpellier

In The South of France

ISVLSI 2015

08–10July2015Montpellier, France

Registration & Payment

About

ISVLSI 2015

08 - 10 July 2015, Montpellier. France

Featuring contributions focused on the emerging trends and novel ideas and concepts in the area of VLSI.

The Vision

Seeking

Details

Early Registration Countdown

Author Information and News

Technical Program

Student Travel Grants and Awards:

Call for Papers

Submission Guidelines:

Important Dates:

Tracks

Special Sessions Call:

Important Dates:

Request

Due: January 20, 2015

Important Dates:

PhD Forum

ISVLSI 2015 Ph.D Forum

Eligibility

Selection

Benefit to selected students

Author Information

Important Dates

Venue

The Symposium Will Be Held At

Faculte de Medecine

Getting Here

By Air

Getting To Town

By Train

Hotels / Accommodations

Keynote Speakers

Keynote Speakers

Heike Riel

IBM Research – Zurich

The Future of Nanoelectronics: New Materials, Architectures and Devices

Tanya Nigam and Andreas Kerber

GLOBALFOUNDRIES

Enabling scaling of advanced CMOS technologies: A reliability perspective

Sponsors

Sponsorship plays a major role in the success of ISVLSI

Organizing Committee

General Chairs

Program Chairs

Publication Chairs

Financial Chair

Local Arrangement Chair

Special Session Chairs

Web Chairs

Registration Chair

Industrial Liaison Chair

Ph.D. Forum Co-Chairs

Publicity Chairs

International Liaison Chairs

Steering Committee Chair

Technical Program Committee

Analog and Mixed-Signal Circuits (AMS)

Chairs

Members

Computer Aided Design and Verification (CAD)

Chairs

Members

Digital Circuits and FPGA based Designs (DCF)

Chairs

Members

Emerging and post-CMOS Technologies (EPT)

Chairs

for a Wonderful ISVLSI 2015
Check out the Photo Gallery and Closing Remarks