10:00 AM

A New Process Variation Monitoring Circuit

Davit Mirzoyan and Ararat Khachatryan

10:20 AM

Mixed-Signal Design Using Digital CAD

Vishnu Unnikrishnan and Mark Vesterbacka

10:40 AM

An Integrated Current Mode CTLE Receiver Front End with Charge Mode Adaptation

Divya Duvvuri and Vijaya Sankara Rao Pasupureddi

10:00 AM

An Automated Hardware/Software Co-Design  Flow for Partially Reconfigurable FPGAs

Shaon Yousuf and Ann Gordon-Ross

10:20 AM

Angel-Eye: A Complete Design Flow for Mapping CNN onto Customized Hardware

Kaiyuan Guo, Lingzhi Sui, Jiantao Qiu, Song Yao, Song Han, Yu Wang and Huazhong Yang

10:40 AM

FPGA Based Cyber Security Protocol for Automated Traffic Monitoring Systems: Proposal and Implementation

Anupam Chattopadhyay, Vikramkumar Pudi, Anubhab Baksi and Thambipillai Srikanthan

11:00 AM

Speeding up Incremental Legalization with Fast Queries to Multidimensional Trees

Renan Netto, Vinicius Livramento, Chrystian Guth, Luiz C. V. Dos Santos and Jose Luis Güntzel

11:20 AM

Timing Analysis and Optimization Based on Flexible Flip-Flop Timing Model

Jeongwoo Heo and Taewhan Kim

11:40 AM

Synthesizing Asynchronous Circuits Toward Practical Use

Heechun Park and Taewhan Kim

11:00 AM

Next Generation Automotive Architecture Modeling and Exploration for Autonomous Driving

Bowen Zheng, Hengyi Liang, Qi Zhu, Huafeng Yu and Chung-Wei Lin

11:20 AM

Online Unusual Behavior Detection for Temperature Sensor Networks

Hengyang Zhao, Sheldon X.-D. Tan, Hai Wang, and Hai-Bao Chen

11:40 AM

Security Challenges in CPS and IoT: from End-Node to the System

Kelvin Ly and Yier Jin

2:30 PM

VLSI Architecture for Cyclostationary Feature Detection based Spectrum Sensing for Cognitive-Radio Wireless Networks and Its ASIC Implementation

Mahesh S. Murty and Rahul Shrestha

2:50 PM

Generating Multi-Cycle and Multiple Transient Fault Resilient Design during Physically Aware High Level Synthesis

Anirban Sengupta and Deepak Kachave

3:10 PM

Power-Performance Optimization of a Virtualized SMT Vector Processor via Thread Fusion and Lane Configuration

Yaojie Lu, SeyedAmin Rooholamin, and Sotirios G. Ziavras

2:30 PM

Neuromorphic Computing from the Computer Science Perspective

Catherine D. Schuman

2:50 PM

A VLSI Design for Neuromorphic Computing

Mark E. Dean and Christopher Daffron

3:10 PM

Reducing the Model Order of Deep Neural Networks Using Information Theory

Ming Tu, Visar Berisha, Yu Cao, and Jae-Sun Seo

3:30 PM

A Reconfigurable Array Architecture for NML

G. Causapruno, U. Garlando, F. Cairo, M. Zamboni, and M. Graziano

3:50 PM

Design and Analysis of Novel InSb/Si Heterojunction Double Gate Tunnel Field Effect Transistor

S. Ahish, Dheeraj Sharma, M. H. Vasantha, and Y. B. N. Kumar

4:10 PM

A Memristor Crossbar Based Computing Engine Design Optimized for High Speed and Accuracy

Chenchen Liu, Qing Yang, Bonan Yan, Jianlei Yang, Xiaocong Du, Weijie Zhu, Hao Jiang, Qing Wu, Mark Barnell and Hai Li

3:30 PM

Design of Division Circuits for Stochastic Computing

Te-Hsuan Chen and John P. Hayes

3:50 PM

Adaptive Filter Design using Stochastic Circuits

Honglan Jiang, Chengkun Shen, Pieter Jonker, Fabrizio Lombardi and Jie Han

4:10 PM

High-Accuracy FIR Filter Design using Stochastic Computing

Bo Yuan and Yanzhi Wang

4:45 PM

Design and Characterization of the TERO-PUF on SRAM FPGAs

Cédric Marchand, Lilian Bossuet and Abdelkarim Cherkaoui

5:05 PM

Hardware/Software Isolation and Protection Architecture for Transparent Security

Enforcement in Networked Devices Festus Hategekimana, Pierre Nardin and Christophe Bobda

5:25 PM

A Gracefully Degrading and Energy-Efficient Fault Tolerant NoC Using Spare Core

B. Naresh Kumar Reddy, M. H. Vasantha, and Y. B. Nithin Kumar

4:45 PM

Analyzing Imprecise Adders Using BDDs — A Case Study Cunxi Yu and Maciej Ciesielski

5:05 PM

Post-Placement Optimization for Thermal-induced Mechanical Stress Reduction

Tiantao Lu, Zhiyuan Yang and Ankur Srivastava

5:25 PM

Impact of VT and Body-Biasing on Resistive short detection in 28nm UTBB FDSOI – LVT and RVT configurations

Amit Karel, Mariane Comte, Jean-Marc Galliere, Florence Azais, and Michel Renovell

10:00 AM

Low Cost VLSI Architecture for Sample Adaptive Offset Encoder in HEVC

Sayed El Gendy, Ahmed Shalaby, and Mohammed S. Sayed

10:20 AM

Dynamic Per-warp Reconvergence Stack for Efficient Control Flow Handling in GPUs

Yaohua Wang, Xiaowen Chen, Dong Wang, and Sheng Liu

10:40 AM

Subthreshold Passive RFID Tag's Baseband Processor Core Design with Custom

Modules and Cells

Weiwei Shi, Zhao Guangdong, and Chiu-Sing Choy

10:00 AM

Selective Enhancement of Randomness at the Materials Level: Poly-Si Based Physical Unclonable Functions (PUFs)

Hao-Ting Shen, Fahim Rahman, Bicky Shakya, Mark Tehranipoor, and Domenic Forte

10:20 AM

A Designer’s Rationale for Nanoelectronic Hardware Security Primitives

Garrett S. Rose, Mesbah Uddin, and Md. Badruddoja Majumder

10:40 AM

Hardware Security Challenges Beyond CMOS: Attacks and Remedies

Kaveh Shamsi, Wujie Wen, and Yier Jin

11:00 AM

Attacking an SRAM-based PUF through Wearout

Alec Roelke and Mircea R. Stan

11:20 AM

Techniques for Improved Reliability in Memristive Crossbar PUF Circuits

Mesbah Uddin, Md. Badruddoja Majumder, Garrett S. Rose, Karsten Beckmann,

Harika Manem, Zahiruddin Alamgir, and Nathaniel C. Cady

11:40 AM

LLPA: Logic state based Leakage Power Analysis

Siva Nishok Dhanuskodi, Shahrzad Keshavarz and Daniel Holcomb

11:00 AM

Hardware Design Automation of Convolutional Neural Networks

Andrea Solazzo, Emanuele Del Sozzo, Irene De Rose, Matteo De Silvestri,

Gianluca C. Durelli, and Marco D. Santambrogio

11:20 AM

Low-Power Wearable System for Real-Time Screening of Obstructive Sleep Apnea

Grégoire Surrel, Francisco Rincón, Srinivasan Murali and David Atienza

11:40 AM

YodaNN: An Ultra-Low Power Convolutional Neural Network Accelerator Based on Binary Weights

Renzo Andri, Lukas Cavigelli, Davide Rossi and Luca Benini

2:15 PM

Workload-aware Power Gating Design and Run-time Management for Massively Parallel GPGPUs

Kapil Dev, Sherief Reda, Indrani Paul, Wei Huang and Wayne Burleson

2:35 PM

Write Pulse Scaling for Energy Efficient STT-MRAM

Yousra Alkabani, Zach Koopmans, Haifeng Xu, Alex K. Jones, and Rami Melhem

2:55 PM

Hardware Trust through Layout Filling: a Hardware Trojan Prevention Technique

Papa-Sidy Ba, Sophie Dupuis, Manikandan Palanichamy, Marie-Lise Flottes, Giorgio Di Natale and Bruno Rouzeyre

2:15 PM

Computing in Ribosomes: Performing Boolean Logic Using mRNA-Ribosome System

Pratima Chatterjee, Mayukh Sarkar and Prasun Ghosal

2:35 PM

Efficient Low-Density Parity-Check (LDPC) Code Decoding for Combating Asymmetric Errors in STT-RAM

Bohua Li, Yukui Pei and Wujie Wen

2:55 PM

System Design for In-hardware STDP Learning and Spiking Based Probablistic Inference

Khadeer Ahmed, Amar Shrestha, Yanzhi Wang and Qinru Qiu

3:15 PM

A Hybrid Algorithm to Conservatively Check the Robustness of Circuits

Niels Thole, Görschwin Fey, and Alberto Garcia-Ortiz

3:35 PM

Formal Verification Using Don’t-Care and Vanishing Polynomials Cunxi Yu and Maciej Ciesielski

3:55 PM

Routing-aware Incremental Timing-driven Placement

Jucemar Monteiro, Nima Karimpour Darav, Guilherme Flach, Mateus Fogaça, Ricardo Reis, Andrew Kennings, Marcelo Johann and Laleh Behjat

3:15 PM

Design and Performance Evaluation of Approximate Floating-Point Multipliers

Peipei Yin, Chenghua Wang, Weiqiang Liu and Fabrizio Lombardi

3:35 PM

Energy-Efficient Design of the Secure Better Portable Graphics Compression Architecture  for Trusted Image Communication in the  IoT

Umar Albalawi, Saraju P. Mohanty, and Elias Kougianos

3:55 PM

Energy-Efficient and Secure S-Box circuit using Symmetric Pass Gate Adiabatic Logic

S. Dinesh Kumar, Himanshu Thapliyal, Azhar Mohammad, Vijay Singh and Kalyan S. Perumalla

4:30 PM

Scalable Integer DCT Architecture for HEVC Encoder

Maher Abdelrasoul, Mohammed S. Sayed, and Victor Goulart

4:50 PM

An improved approach for the synthesis of Boolean functions using memristor based IMPLY and INVERSE-IMPLY gates

F. Lalchhandama, Brojo Gopal Sapui, and Kamalika Datta

5:10 PM

Adaptive Overclocking and Error Correction Based on Dynamic Speculation Window Rengarajan Ragavan, Cedric Killian and Olivier Sentieys

5:30 PM

On-chip Delay Measurement Circuit for Reliability Characterization of SRAM

Pankaj Verma, Rohit Halba, Hemant Patel and Maryam Shojaei Baghini

4:30 PM

Digital LDO with Time-Interleaved Comparators for Fast Response and Low Ripple

Saurav Maji, Sohail Ahasan, Saurav Maji, Kaushik Roy, and Mrigank Sharad

4:50 PM

Design of Low Power 5-bit Hybrid Flash ADC

S. M. Mayur, R. K. Siddharth, Y. B. Nithin Kumar, and M. H. Vasantha

5:10 PM

An Accurate All CMOS Temperature Sensor for IoT Applications Sunil Kumar Maddikatla and Srivatsava Jandhyala

5:30 PM

Design of Low-Power High-Gain Operational Amplifier for Bio-Medical Applications           

Sanjay Singh Rajput, Ashish Singh, Ashwani K. Chandel, and Rajeevan Chandel

P1.

A Compact Set of Seeds for LFSR-Based Test Generation from a Fully-Specified Compact Test Set

Irith Pomeranz

P2.

Low-power and High Performance Sinusoidal Clocked Dynamic Circuit Design

Raghava Katreepalli, Hemanth Chemanchula, Themistoklis Haniotakis, and Yiorgos Tsiatouhas

P3.

Approximate Adder with Hybrid Prediction and Error Compensation Technique

Xinghua Yang, Yue Xing, Fei Qiao, Qi Wei and Huazhong Yang

P4.

SecCheck: A Trustworthy System with Untrusted Components       

Rajshekar Kalayappan and Smruti R. Sarangi

P5.

A Multi-Accuracy-Level Approximate Memory Architecture Based on Data Significance Analysis

Yuanchang Chen, Xinghua Yang, Fei Qiao, Jie Han, Qi Wei, and Huazhong Yang

P6.

On Area-Efficient Implementation of Data Delays in 7 Series Xilinx FPGAs

Marek Parfieniuk and Sang Yoon Park

P7.

Phase-based Dynamic Instruction Window Optimization for Embedded Systems

Tosiron Adegbija and Ann Gordon-Ross

P8.

Skybridge-3D-CMOS: A Vertically-Composed Fine-Grained 3D CMOS Integrated Circuit Technology

Mingyu Li, Jiajun Shi, Mostafizur Rahman, Santosh Khasanvis, Sachin Bhat and Csaba Andras Moritz

P9.

Fault-tolerant FPGA with Column-based Redundancy and Power Gating Using RRAM

Kibum Lee and S. Simon Wong

P10.

Accurate Synthesis of Arithmetic Operations with Stochastic Logic

Ensar Vahapoğlu and Mustafa Altun

P11.

A Low-Leakage, Robust ESD Clamp with Thyristor Delay Element in 65nm CMOS Technology

Mahdi Elghazali, Manoj Sachdev and Ajoy Opal

P12.

Mod (2P-1) Shuffle Memory-Access Instructions for FFTs on Vector SIMD DSPs

Sheng Liu, Hanyan Chen, Jianghua Wan, and Yaohua Wang

P13.

Energy Optimization of Racetrack Memory-Based SIMON Block Cipher       

Suman Deb, Anupam Chattopadhyay and Hao Yu

P17.

Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays

Muhammed Ceylan Morgül, Furkan Peker and Mustafa Altun

P18.

Threshold-Dependent Camouflaged Cells to Secure Circuits Against Reverse Engineering Attacks

Maria I. Mera Collantes, Mohamed El Massad, and Siddharth Garg

P19.

On the Design of Ultra-High Density 14nm Finfet based  Transistor-Level Monolithic 3D ICs

Jiajun Shi, Deepak Nayak, Motoi Ichihashi, Srinivasa Banna and Csaba Andras Moritz

P20.

A Real-Time and Energy-Efficient Implementation of Difference-of-Gaussian with Flexible Thin-Film Transistors

Nan Wu, Zheyu Liu, Fei Qiao, Qi Wei, Xiaojun Guo, Yuan Xie, and Huazhong Yang

P21.

A Configurable and Lightweight Timing Monitor for Fault Attack Detection

Chinmay Deshpande, Bilgiday Yuce, Nahid Farhady Ghalaty, Dinesh Ganta, Patrick Schaumont and Leyla Nazhandali

P22.

Gate Overdrive with Split-circuit Biasing to Substitute for Body Biasing in FinFET and UTB FDSOI Circuits

Andrew Whetzel and Mircea R. Stan

P23.

Analysis of Switching Energy and Delay for Magnetic Logic Devices

Madhav Rao and Neha Oraon

P24.

A 90-nm CMOS Frequency Synthesizer with a Tripler for 60-GHz Wireless

Communication Systems

Po-Tsang Chen and Ching-Yuan Yang

P25.

A System-Level Exploration of Power Delivery Architectures for Near-Threshold Manycores Considering Performance Constraints

Ioannis Stamelakos, Amin Khajeh, Ahmed Eltawil, Gianluca Palermo, Cristina Silvano,

and Fadi Kurdahi  

P26.

Fault-tolerant Clock Synchronization with High Precision    

Attila Kinali, Florian Huemer, and Christoph Lenzen

P27.

STA: A Highly Scalable Low Latency Butterfly Fat Tree Based 3D NoC Design

Avik Bose, Prasun Ghosal, and Saraju P. Mohanty

P28.

Leveraging Compiler Support on VLIW processors for Efficient Power Gating

Juan S. P. Giraldo, Luigi Carro, Stephan Wong, and Antonio C. S. Beck 

P29.

MINLP based Power Optimization for Pipelined ADC

A. Purushothaman

P30.

Voice Based User-Device Physical Unclonable Functions for Mobile Device Authentication

Yunxi Guo and Akhilesh Tyagi

P31.

Taylor Series Based Architecture for Quadruple Precision Floating Point Division  

Manish Kumar Jaiswal and Hayden K.-H. So

P32.

An Accurate All CMOS Bandgap Reference Voltage with Integrated Temperature Sensor for IoT Applications

Sunil Kumar Maddikatla and Srivatsava Jandhyala

P33.

Thermal-aware Preemptive Test Scheduling for Network-on-Chip based 3D ICs

Kanchan Manna, Chatla Swamy Sagar, Santanu Chattopadhyay, and Indranil Sengupta

P34.

Design Optimization of Register File Throughput and Energy using a Virtual Prototyping (ViPro) Tool

Ningxi Liu and Benton Calhoun

P35.

A Learning-based Approach to Secure JTAG against Unseen Scan-based Attacks

Xuanle Ren, R. D. (Shawn) Blanton, and Vítor Grade Tavares

P36.

Using Statistical Models to Improve the Reliability of Delay-Based PUFs

Xiaolin Xu, Wayne Burleson, and Daniel E. Holcomb

P37.

Fast Multi-Level Test Generation at the RTL

Kelson Gent and Michael S. Hsiao

P38.

Architecture Exploration for Energy-Efficient Embedded Vision Applications: From

General Purpose Processor to Domain Specific Accelerator

Maria Malik, Farnoud Farahmand, Paul Otto, Nima Akhlaghi, Tinoosh Mohsenin,

Siddhartha Sikdar, and Houman Homayoun

P39.

DSD: A Dynamic State-Deflection Method for Gate-Level Netlist Obfuscation

Jaya Dofe, Yuejun Zhang and Qiaoyan Yu  

P40.

Soft Error Effect Tolerant Temporal Self-Voting Checkers: Energy vs. Resilience

Tradeoffs

Faris S. Alghareb, Mingjie Lin, and Ronald F. DeMara

P41.

Accurus: A Fast Convergence Technique for Accuracy Configurable Approximate Adder Circuits

Vinamra Benara and Suresh Purini 

F1.

Thermal-Aware Design and Test Techniques for Two-and Three-Dimensional

Networks-on-Chip

Kanchan Manna, Santanu Chattopadhyay, and Indranil Sengupta

F2.

A Low-Cost Mixed Clock Generator for High Speed Adiabatic Logic

Zhou Zhao, Ashok Srivastava, Lu Peng, and Saraju P. Mohanty

F3.

Accelerating Particle Filter on FPGA

B. G. Sileshi, J. Oliver, and C. Ferrer

F4.

Soft-Error Tolerant Datapath Synthesis Considering Adjacency Constraint

between Components

Junghoon Oh and Mineo Kaneko

10:00 AM

Gossip NoC - Avoiding Timing Side-Channel Attacks through Traffic Management

Cezar Reinbrecht, Altamiro Susin, Lilian Bossuet, and Johanna Sepúlveda

10:20 AM

Leakage Power Aware Task Assignment Algorithms for Multicore Platforms

Gayathri Ananthanarayanan, Smruti R. Sarangi and M. Balakrishnan

10:40 AM

A Design Space Exploration Methodology for Parameter Optimization in Multicore Processors

Prasanna Kansakar and Arslan Munir

10:00 AM

Reliable Many-Core System-on-Chip Design using K-Node Fault Tolerant Graphs Zheng Wang, Alessandro Littarru, Emmanuel Ikechukwu Ugwu, Shazia Kanwal and Anupam Chattopadhyay

10:20 AM

Seamlessly Pipelined Shift-and-Add Circuits Based on Precise Delay Analysis and Its Applications

Tso-Bing Juang and Ying-Ren Lee

10:40 AM

On Time Redundancy of Fault Tolerant C-Based MPSoCs

Anjana Balachandran, Nandeesh Veeranna and Benjamin Carrion Schafer

11:00 AM

Cost and Thermal Analysis of High-Performance 2.5D and 3D Integrated Circuit Design Space 

Dylan Stow, Itir Akgun, Russell Barnes, Peng Gu and Yuan Xie

11:20 AM

Memristor-Based Discrete Fourier Transform for Improving Performance and Energy

Efficiency

Ruizhe Cai, Ao Ren, Yanzhi Wang and Bo Yuan

11:40 AM

Device Circuit Co Design of FEFET Based Logic for Low Voltage Processors

Sumitha George, Ahmedullah Aziz, Xueqing Li, Moon Seok Kim, Suman Datta,

John Sampson, Sumeet Gupta, and Vijaykrishnan Narayanan

11:00 AM

A Scalable Design Approach to Efficiently Map Applications on CGRAs

Satyajit Das, Thomas Peyret, Kevin Martin, Gwenolé Corre, Mathieu Thevenin,

and Philippe Coussy

11:20 AM

SoC, NoC and Hierarchical Bus Implementations of Applications on FPGAs Using

the FCUDA Flow

Tan Nguyen, Yao Cheny, Kyle Rupnow, Swathi Gurumani, and Deming Chen

11:40 AM

Area Efficient Hardware Architecture for Implicitly-Defined Complex Events

Processing

Mohammad Tahghighi, Wei Zhang, and Sharad Sinha

1:00 PM

Design Space Exploration of FinFETs with Double Fin Heights for Standard Cell Library

Chi-Hung Lin, Chia-Shiang Chen, Yu-He Chang, Yu-Ting Zhang, Shang-Rong Fang, Santanu Santra and Rung-Bin Lin

1:20 PM

Multiple-Bit-Flip Detection Scheme for A Soft-Error Resilient TCAM

Infall Syafalni, Tsutomu Sasao and Xiaoqing Wen

1:40 PM

A Comparative Study of Si/Ge and GaSb/InAs Tunnel FET-based Cellular Neural Network

Amit Ranjan Trivedi and Susmita Dey Manasi

1:00 PM

A Dual-Threshold Voltage Approach for Timing Speculation in CMOS Circuits

Xiaowen Wang and William H. Robinson

1:20 PM

Multi Clock Flooded LDPC Decoding Architecture with Reduced Memory and Interconnect

Oana Boncalo and Ioana Mot

1:40 PM

The Impact of Heterogeneity on a Reconfigurable Multicore System

Rafael Fão de Moura, Jeckson Dellagostin Souza, Luigi Carro, Antonio Carlos Schneider Beck, and Mateus Beck Rutzig

2:00 PM

A Pruning Technique for B&B based Design Exploration of Approximate Computing Variants

Mario Barbareschi, Federico Iannucci and Antonino Mazzeo

2:20 PM

Stochastic-Based Convolutional Networks with Reconfigurable Logic Fabric

Mohammed Alawad and Mingjie Lin

2:40 PM

A Ternary-valued, Floating Gate Transistor-based Circuit Design Approach

Monther Abusultan and Sunil P. Khatri

2:00 PM

Quantification of Sense Amplifier Offset Voltage Degradation due to Zero- and Run-time Variability

Innocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Praveen Raghavan, Francky Catthoor and Wim Dehaene

2:20 PM

Improving the Functional Test Delay Fault Coverage: A Microprocessor Case Study

A. Touati, A. Bosio, P. Girard, A. Virazel, P. Bernardi, and M. Sonza Reorda

2:40 PM

Joint Soft-Error-Rate (SER) Estimation for Combinational Logic and Sequential Elements

Ji Li and Jeffrey Draper