9:50 AM

Gyrator-C based Bandpass Filter with Improved Dynamic Range for Fully Integrated RF Front-end

Lakshmi N S and Bhaskar M

10:10 AM

Replica-Based Low Drop-Out Voltage Regulator with Assistant Power Transistors for Digital VLSI Systems

Yang Nan, Chenchang Zhan, Guanhua Wang, Linjun He and Han Li

10:30 AM

Area Efficient NMOS based Positive and Negative Voltage Multiplier

Vikas Rana

9:50 AM

Achieving Low Power Classification with Classifier Ensemble

Fanglei Hu, Min Zhang and Hailong Jiao

10:10 AM

A Power-efficient Hybrid Architecture Design for Image Recognition using CNNs

Jinhang Choi, Srivatsa Srinivasa, Yasuki Tanabe, Jack Sampson and Vijaykrishnan Narayanan

10:30 AM

Towards Budget-Driven Hardware Optimization for Deep Convolutional Neural Networks using Stochastic Computing

Zhe Li, Ji Li, Ao Ren, Caiwen Ding, Jeffrey Draper, Qinru Qiu, Bo Yuan and Yanzhi Wang

9:50 AM

*Fast heuristics for near-optimal signal restoration in post-silicon validation

Xiaobang Liu and Ranga Vemuri

10:10 AM

PGIREM: Reliability-Constrained IR Drop Minimization and Electromigration Assessment of VLSI Power Grid Networks using Cooperative Coevolution

Sukanta Dey, Satyabrata Dash, Sukumar Nandi and Gaurav Trivedi

10:30 AM

Silicon Debug with Maximally Expanded Internal Observability using Nearest Neighbor Algorithm

Ankit Jindal, Binod Kumar, Nitish Jindal, Masahiro Fujita and Virendra Singh

10:50 AM

Application Specific Networks-on-Chip Synthesis: An Energy Efficient Approach

Somayeh Kashi, Ahmad Patooghy, Dara Rahmati, Mahdi Fazeli and Michel Kinsy

11:10 AM

Accurate Models for Optimizing Tapered Microchannel Heat Sinks in 3D ICs

Leslie Hwang, Beomjin Kwon and Martin Wong

11:30 AM

Designing and Benchmarking of Double-Row Height Standard Cells

Yu-Xiang Chiang, Cheng-Wei Tai, Shang-Rong Fang, Kai-Chun Peng, Yuan-Dar Chung, Jin-Kai Yang and Rung-Bin Lin

10:50 AM

Dual-Threshold Directed Execution Progress Maximization for Nonvolatile Processors

Dongqin Zhou, Keni Qiu, Yuanchao Xu, Xin Shi and Yongpan Liu

11:10 AM

*A Comprehensive Electro-Optical Model for Silicon Photonic Switches

Xuanqi Chen, Zhifei Wang, Yi-Shing Chang, Jiang Xu, Peng Yang, Zhehui Wang and Luan H.K. Duong

11:30 AM

CMOS Gates with Second Function

Jan Nevoral, Richard Ruzicka and Vaclav Simek

10:50 AM

Tagless DRAM Cache

S R Swamy Saranam Chongala and Madhu Mutyam

11:10 AM

CT-Cache: Compressed Tag-Driven Cache Architecture

Haeyoon Cho, Joonho Kong, Arslan Munir and Naresh Kumar Giri

11:30 AM

High Bandwidth Off-Chip Memory Access Through Hybrid Switching and Inter-Chip Wireless Links

Sri Harsha Gade, Hemanta Kumar Mondal and Sujay Deb

3:50 PM

Investigating Reliability and Security of Integrated Circuits and Systems

Qiaoyan Yu, Zhiming Zhang, and Jaya Dofe.

4:10 PM

Reliability and Security in Non-volatile Processors, Two Sides of the Same Coin

Patrick Cronin, Chengmo Yang, and Yongpan Liu

4:30 PM

A Short Survey at the Intersection of Reliability and Security in Processor Architecture Designs

Lake Bu, Miguel Mark, and Michel Kinsy

4:50 PM

Can Soft Errors Be Handled Securely?

Senwen Kan, Jennifer Dworak

3:50 PM

*BD-NET: A Multiplication-less DNN with Binarized Depthwise Separable Convolution

Zhezhi He, Shaahin Angizi, Adnan Siraj Rakin and Deliang Fan

4:10 PM

TaiJiNet : Towards Partial Binarized Convolutional Neural Network for Embedded Systems

Yingjian Ling, Kan Zhong, Yunsong Wu, Duo Liu, Jinting Ren, Renping Liu, Moming Duan, Weichen Liu and Liang Liang

4:30 PM

An ECC-Free MLC STT-RAM based Approximate Memory Design for Multimedia Applications

Zihao Liu, Tao Liu, Jie Guo, Nansong Wu and Wujie Wen

4:50 PM

Robust Timing Attack Countermeasure on Virtual Hardware

Kai Yang, Jungmin Park, Mark Tehranipoor and Swarup Bhunia

3:50 PM

Towards Theoretical Cost Limit of Stochastic Number Generators for Stochastic Computing

Meng Yang, Bingzhe Li, David J. Lilja, Bo Yuan and Weikang Qian

4:10 PM

An Energy-Efficient PIM-Accelerator Simulation Framework

Di Gao, Tianhao Shen, Cheng Zhuo

4:30 PM

Efficient Self-balancing Binary Search Tree for Non-Volatile Memory with Write Asymmetry

Ming-Chang Yang

4:50 PM

Minimizing the Energy Consumption of MLC STT-RAM Main Memory with Asymmetric Write Energy by Re-designing Cache Management
Tseng-Yi Chen

P1.

Fully-on-Chip Digitally Assisted LDO Regulator with Improved Regulation and Transient Responses

Han Li, Chenchang Zhan and Ning Zhang

P2.

A Novel Asynchronous Analog to Digital Converter for Surveillance Camera Applications

Siddharth Kala, Sunil R., Nithin Kumar Y.B., Vasantha M.H. and Edoardo Bonizzoni

P3.

An Integrated MaxFit Genetic Algorithm-SPICE Framework for 2-stage Op-amp Design Automation

Harsha M. V. and B. P. Harish

P4.

Mismatch Resilient 3.5-bit MDAC with MCS-CFCS

Satyajit Mohapatra, Hari Gupta and Nihar Mohapatra

P5.

Design of Low Power SAR ADC using Clock Retiming

Jalaja S and Vijaya Prakash A M

P6.

A 375 nA Input Off Current Schmitt Triger LDO for Energy Harvesting IoT Sensors

Koichiro Ishibashi and Shiho Takahashi

P7.

Precise Duty Cycle Variation Detection and Self-Calibration System for High-Speed Data Links

Karen Khachikyan, Abraham Balabanyan and Hrachya Gumroyan

P8.

Parametric Circuit Optimization with Reinforcement Learning

Changcheng Tang, Zuochang Ye and Yan Wang

P9.

End-to-End Industrial Study of Retiming

Cunxi Yu, Chau-Chin Huang, Gi-Joon Nam, Mihir Choudhury, Victor N. Kravets, Andrew Sullivan, Maciej Ciesielski and Giovanni De Micheli

P10.

Communication-aware Module Placement for Lowering Power in Large FPGA Designs

Kalindu Herath, Alok Prakash, Udaree Kanewala and Thambipillai Srikanthan

P11.

A novel mixed-size fixed-ouline floorplacement algorithm

Qian Chen and Sheqin Dong

P12.

ARCHVerifyr: An Embedded Software-Driven Approach for Architecture Verification

Tomas Grimm, Djones Lettnin and Michael Huebner

P13.

High-average and Guaranteed Performance for Wireless Networks-on-Chip Architectures

Mohammad Baharloo, Ahmad Khonsari, Pouya Shiri, Iman Namdari and Dara Rahmati

P14.

Hardware Implementation of Reconfigurable Separable Convolution

Lei Rao, Bin Zhang and Jizhong Zhao

P15.

Low Overhead Online Checkpoint for Intermittently Powered Non-volatile FPGAs

Xinyi Zhang, Clay Patterson, Yongpan Liu, Chengmo Yang, Chun Jason Xue and Jingtong Hu

P16.

Pixel-Parallel Architecture for Neuromorphic Smart Image Sensor with Visual Attention

Md Jubaer Hossain Pantho, Pankaj Bhowmik and Christophe Bobda

P17.

Lightweight ASIC Implementation of AEGIS-128

Anubhab Baksi, Vikramkumar Pudi, Swagata Mandal and Anupam Chattopadhyay

P18.

Architecture Exploration and Delay Minimization Synthesis for SET-Based Programmable Gate Arrays

Chia-Cheng Wu, Kung-Han Ho, Juinn-Dar Huang and Chun-Yao Wang

P19.

MRAM-on-FDSOI Integration: A Bit-cell Perspective

Hao Cai, You Wang, Wang Kang, Lirida Naviner, Xinning Liu, Jun Yang and Weisheng Zhao

P20.

High Performance Ternary Multiplier using CNTFET

Subhendu Kumar Sahoo, Krishna Dhoot, and Rasmita Sahoo

P21.

A Robust Dual Reference Computing-in-Memory Implementation and Design Space Exploration Within STT-MRAM

Liuyang Zhang, Wang Kang, Hao Cai, Peng Ouyang, Lionel Torres, Youguang Zhang, Aida Todri-Sanial and Weisheng Zhao

P22.

Biosensing performance optimization of DMFET for fully filled and partially filled cavity

Ankita Porwal and Chitrakant Sahu

P23.

A Dynamic Resource Allocation Strategy for NoC Based Multicore Systems with Permanent Faults

Suraj Paul, Navonil Chatterjee and Prasun Ghosal

P24.

Floorplanning in Graphene Nanoribbon (GNR) Based Circuits

Subrata Das and Debesh Das

P25.

Generating Safety Guidance for Medical Injection with Three-Compartment Pharmacokinetics Model

Cunxi Yu, Heinz Riener, Francesca Stradolini and Giovanni De Micheli

P26.

A Novel Approach for Nearest Neighbor Realization of 2D Quantum Circuits

Anirban Bhattacharjee, Chandan Bandyopadhyay, Robert Wille, Rolf Drechsler and Hafizur Rahaman

P27.

A Hardware-efficient Implementation of CLOC for On-Chip Authenticated Encryption

Mahmoud A. Elmohr, Sachin Kumar, Mustafa Khairallah and Anupam Chattopadhyay

P28.

0.9 to 2.5 GHz Sub-sampling Receiver Architecture for Dynamically Reconfigurable SDR

Ajinkya Kale, Johannes Sturm and Vijaya Sankara Rao Pasupureddi

P29.

Hardware Obfuscation using Strong PUFs

Soroush Khaleghi and Wenjing Rao

P30.

Multi-Block APUF with 2-level Voltage Supply

Yunxi Guo, Timothy Dee and Akhilesh Tyagi

P31.

Write energy optimization for STT-MRAM cache with data pattern characterization

Bi Wu, Xiaolong Zhang, Yuanqing Cheng, Zhaohao Wang, Dijun Liu, Youguang Zhang and Weisheng Zhao

P32.

Time Stamp Based Scheduling for Energy Harvesting Systems with Hybrid Nonvolatile Hardware Support

Xin Shi, Tongda Wu, Keni Qiu, Huazhong Yang and Yongpan Liu

P33.

EETD: An Energy Efficient Design for Runtime Hardware Trojan Detection in Untrusted Network-on-Chip

Mubashir Hussain, Amin Malekpour, Hui Guo and Sri Parameswaran

P34.

Combining Symbolic Computer Algebra and Boolean Satisfiability for Automatic Debugging and Fixing of Complex Multipliers

Alireza Mahzoon, Daniel Grosse and Rolf Drechsler

P35.

Enhancing lifetime of PCM-based main memory with Efficient Recovery of Stuck-at Faults

Marjan Asadinia and Christophe Bobda

F1.

Guessing your PIN right: Unlocking smartphones with publicly available sensor data

David Berend, Bernhard Jungk and Shivam Bhasin

F2.

Synthesis, Technology Mapping and For Emerging Technologies

Debjyoti Bhattacharjee and Anupam Chattopadhyay

F3.

Logic Synthesis for In-Memory Computing using Resistive Memories

Saeideh Shirinzadeh and Rolf Drechsler

F4.

Minimalistic Perspective to Public Key Implementations on FPGA

Debapriya Basu Roy and Debdeep Mukhopadhyay

F5.

Development of high-stability, low-leakage 6Tr-SRAM with single data line and single power supply using SOTB process

Shin Miyamoto and Nobuaki Kobayashi

F6.

Exploiting Principle of Moving Target Defense to Secure FPGA Systems

Zhiming Zhang and Qiaoyan Yu

9:50 AM

A Highly Flexible Lightweight and High Speed True Random Number Generator on FPGA

Faqiang Mei, Lei Zhang, Chongyan Gu, Yuan Cao, Chenghua Wang and Weiqiang Liu

10:10 AM

LUT-Lock: A Novel LUT-based Logic Obfuscation for FPGA-Bitstream and ASIC-Hardware Protection

Hadi Mardani Kamali, Kimia Zamiri Azar, Kris Gaj, Houman Homayoun and Avesta Sasan

10:30 AM

ArtiFact: Architecture and CAD Flow for Efficient Formal Verification of SoC Security Policies

Atul Prasad Deb Nath, Swarup Bhunia and Sandip Ray

9:50 AM

*Identifying Lithography Weak-points of Standard Cells with Partial Pattern Matching

Yongfu Li, I-Lun Tseng, Zhao Chuan Lee, Valerio Perez, Vikas Tripathi and Jonathan Yoong Seang Ong

10:10 AM

Feature Based Coverage Analysis of AMS Circuits

Antara Ain, Akshay Mambakam and Pallab Dasgupta

10:30 AM

SAT Encoding-based Verification of Sneak Path Problem in Via-switch FPGA

Ryutaro Doi and Masanori Hashimoto

9:50 AM

RRAM Based Buffer Design for Energy Efficient CNN Accelerator

Kaiyuan Guo, Jincheng Yu, Xuefei Ning, Yiming Hu, Yu Wang and Huazhong Yang

10:10 AM

A Mixed-Mode Neuron with On-Chip Tunability for Generic Use in Memristive Neuromorphic Systems

Sagarvarma Sayyaparaju, Ryan Weiss and Garrett S. Rose

10:30 AM

Harnessing Emerging Technology for Compute-In-Memory Support

Nicholas Jao, Akshay Krishna Ramanathan, Srivatsa Srinivasa, Sumitha George, John Sampson, and Vijaykrishnan Narayanan

10:50 AM

91 dB Dynamic Range 9.5 nW Low Pass Filter for Bio-Medical Applications

Jayaram Reddy M K, Sreenivasulu Polineni and Laxminidhi Tonse

11:10 AM

*A Low Power, High Gain Semi-Floating Gate Amplifier for Resonating Sensors Front-End

Luca Marchetti, Yngvar Berg and Mehdi Azadmehr

11:30 AM

A High-Efficient Current-Mode PWM DC-DC Buck Converter Using Dynamic Frequency Scaling

Ankit Rehani, Sujay Deb, Pydi Ganga Bahubalindruni, Bhavin Odedara and Srikanth Bojja

10:50 AM

An Adversarial Example Restoration System for Neuromorphic Computing Security

Chenchen Liu, Qide Dong, Fuxun Yu and Xiang Chen

11:10 AM

MAT: A Multi-strength Adversarial Training Method to Mitigate Adversarial Attacks

Chang Song, Hsin-Pai Cheng, Huanrui Yang, Sicheng Li, Chunpeng Wu, Qing Wu, Yiran Chen and Hai Li

11:30 AM

Hu-Fu: Hardware and Software Collaborative Attack Framework against Neural Networks

Wenshuo Li, Jincheng Yu, Xuefei Ning, Pengjun Wang, Qi Wei, Yu Wang and Huazhong Yang

4:20 PM

Sparse VLSI Layout Feature Extraction: A Dictionary Learning Approach

Hao Geng, Haoyu Yang, Bei Yu, Xingquan Li and Xuan Zeng

4:40 PM

Pattern Similarity Metrics for Layout Pattern Classification and their Validity Analysis by Lithographic Responses

Atsushi Takahashi, Shimpei Sato, Hiroki Ogura, Yu-Min Sung, Ting-Chi Wang

5:00 PM

Recent research and challenges in multiple patterning layout decomposition

Iris Hui-Ru Jiang and Hua-Yu Chang

5:20 PM

Guiding Template-induced Design Challenges in DSA-MP Lithography

Shao-Yun Fang and Kuo-Hao Wu

4:20 PM

*FPAP: A Folded Architecture for Efficient Computing of Convolutional Neural Networks

Yizhi Wang, Jun Lin and Zhongfeng Wang

4:40 PM

Hyperdrive: A Systolically Scalable Binary-Weight CNN Inference Engine for mW IoT End-Nodes

Renzo Andri, Lukas Cavigelli, Davide Rossi and Luca Benini

5:00 PM

An Optimized Architecture For Decomposed Convolutional Neural Networks

Fangxuan Sun, Jun Lin and Zhongfeng Wang

5:20 PM

Interconnect Delay Analysis for RRAM Crossbar based FPGA

Masanori Hashimoto, Yuki Nakazawa, Ryutaro Doi, Jaehoon Yu

4:20 PM

Security challenges in smart surveillance systems and new design opportunities

Hai Li

4:40 PM

Enhancing the Robustness of Deep Neural Networks from ``Smart” Compression

Tao Liu, Zihao Liu, Qi Liu, Wujie Wen

5:00 PM

Accelerating Low Bit-Width Deep Convolution Neural Network in MRAM

Zhezhi He, Shaahin Angizi, Deliang Fan

5:20 PM

Emerging Neuromorphic Computing Paradigms Exploring Magnetic Skyrmions

Sai Li, Wang Kang, Xing Chen, Jinyu Bai, Biao Pan, Youguang Zhang and Weisheng Zhao

9:50 AM

Security-Driven Task Scheduling for Multiprocessor System-on-Chips with Performance Constraints

Nan Wang, Manting Yao, Dongxu Jiang, Song Chen, Yu Zhu

10:10 AM

A Hardware Monitor to Protect Linux System Calls

George Provelengios, Arman Pouraghily, Russell Tessier and Tilman Wolf

10:30 AM

Towards Dynamic Execution Environment for System Security Protection against Hardware Flaws

Kenneth Schmitz, Oliver Keszocze, Jurij Schmidt, Daniel Grosse and Rolf Drechsler

9:50 AM

A Fast and Effective Memristor-Based Method for Finding Approximate Eigenvalues and Eigenvectors of Non-Negative Matrices

Chenghong Wang, Zeinab S. Jalali, Caiwen Ding, Yanzhi Wang and Sucheta Soundarajan

10:10 AM

A Low-Power and Small-Area Multiplier for Accuracy-Scalable Approximate Computing

Hiroyuki Baba, Tongxin Yang, Masahiro Inoue, Kaori Tajima, Tomoaki Ukezono and Toshinori Sato

10:30 AM

A Hardware/Software Co-Design Method for Approximate Semi-supervised K-Means Clustering

Pengfei Huang, Chenghua Wang, Ruizhe Ma, Weiqiang Liu and Fabrizio Lombardi

9:50 AM

Robustness for Smart Cyber Physical Systems and Internet-of-Things: From Adaptive to Intelligent Methods for Reliability and Security

Florian Kriebel, Semeen Rehman, Muhammad Abdullah Hanif, Faiq Khalid, Muhammad Shafique

10:10 AM

On how to efficiently implement Deep Learning algorithms on PYNQ platform

Luca Stornaiuolo, Marco D. Santambrogio, Donatella Sciuto

10:30 AM

Enabling Reliable High Throughput On-Chip Wireless Communication for Many Core Architectures

Sri Harsha Gade, Mitali Sinha, Sidhartha Sankar Rout, Sujay Deb

10:50 AM

Predicting the tolerance of Extreme Electromagnetic Interference on MOSFETs

Nishchay Sule, Troy Powell, Sameer Hemmady and Payman Zarkesh-Ha

11:10 AM

Enhancing Observability for Post-Silicon Debug with On-Chip Communication Monitors

Yuting Cao, Hernan Palombo, Sandip Ray and Hao Zheng

11:30 AM

Performance Enhancement of Split Length Compensated Operational Amplifiers

Donel Anto, Abhijeet D. Taralkar, Nithin Kumar Y. B. and Vasantha M. H.

10:50 AM

Design-Based Fingerprinting Using Side-Channel Power Analysis For Protection Against IC Piracy

James Shey, Naghmeh Karimi, Ryan Robucci and Chintan Patel

11:10 AM

PPAP and iPPAP: PLL based Protection Against Physical attacks

Prasanna Ravi, Shivam Bhasin, Jakub Breier and Anupam Chattopadhyay

11:30 AM

Mystic: Mystifying IP Cores Using an Always-ON FSM Obfuscation Method

Ahmad Patooghy, Ehsan Aerabi, Hamidreza Rezaei, Miguel Mark, Mahdi Fazeli, and Michel A. Kinsy

10:50 AM

FPGA-based Controllers for Compact Low Power Refreshable Braille Display

Suman Muralikrishnan, Pulkit Sapra, Saurabh Agrawal, Piyush Chanana, M. Balakrishnan and P.V.M. Rao

11:10 AM

Very Large-Scale and Node-Heavy Graph Analytics with Heterogeneous FPGA+CPU Computing Platform

Yu Zou and Mingjie Lin

11:30 AM

On-chip Data Security against Untrustworthy Software and Hardware IPs in SoC FPGAs

Sreecharan Gundabolu and Xiaofang Wang

2:30 PM

Design Automation and Test for Flow-Based Biochips: Past Successes and Future Challenges

Tsung-Yi Ho

2:50 PM

Multi-Target Many-Reactant Sample Preparation for Reactant Minimization on Microfluidic Biochips

Yung-Chun Lei, Tien-Kuo Lin, Juinn-Dar Huang

3:10 PM

More Effective Randomly-Designed Microfluidics

Weiqing Ji, Tsung-Yi Ho, Hailong Yao

3:30 PM

Accelerating Simulation of Particle Trajectories in Microfluidic Devices by Constructing a Cloud Database

Junchao Wang, Lingxuan Fu, Liyang Yu, Xiwei Huang, Philip Brisk, William H. Grove r

2:30 PM

PUF-based Secure Test Wrapper for SoC Testing

Sudeendra Kumar, Saurabh Seth, Sauvagya Sahoo, Abhishek Mahapatra, Ayas Kanta Swain, and Kamalakanta Mahapatra

2:50 PM

Detection of Sequential Trojans in Embedded System Designs without Scan Chains

Pranav Dharmadhikari, Akhilesh Raju, Ranga Vemuri

3:10 PM

Designing for Security Within and Between IoT Devices

Mike Borowczak, Rafer Cooley, and Shaya Wolf

3:30 PM

A Two-Tiered Heterogeneous and Reconfigurable Application Processor for Future Internet of Things

Prasanna Kansakar, Arslan Munir

2:30 PM

Glimpse of Domain Control Unit Software Architecture for Intelligent Connected Vehicle

Sun Hua, United Automotive Electronic Systems Co., Ltd

2:50 PM

The challenges of E/E architecture design for EV

Sam QIN, Intron / G-Pulse

3:10 PM

Heterogenous HPC Multi-Core Platforms and Tools

- Functional Intelligence and Digital Integration in Cyber-Physical Systems (CPS)

Juergen Becker, Karlsruhe Institute of Technology

4:10 PM

Solar Cell Based Physically Unclonable Function for Cybersecurity in IoT Devices

S. Dinesh Kumar, Carson Labrado, Riasad Badhan, Himanshu Thapliyal, Vijay Singh

4:30 PM

Designing Scalable Hybrid Wireless NoC for GPGPUs

Hui Zhao, Xianwei Cheng, Saraju P. Mohanty, Juan Fang

4:50 PM

Functional Obfuscation of DSP cores using Robust Logic Locking and Encryption

Anirban Sengupta, Saraju P. Mohanty

4:10 PM

Distributed Timing Analysis at Scale

Martin D. F. Wong, Tsung-Wei Huang

4:30 PM

Timing Macro Modeling for Efficient Hierarchical Timing Analysis

Iris Hui-Ru Jiang, Pei-Yu Lee

4:50 PM

Timing with Virtual Signal Synchronization for Circuit Performance and Netlist Security

Grace Li Zhang, Bing Li, Ulf Schlichtmann

4:10 PM

Realizing Closed-loop, Online Tuning and Control for Configurable-cache Embedded Systems: Progress and Challenges

Islam S. Badreldin, Ann Gordon-Ross, Tosiron Adegbija, Mohammad. H. Alsafrjalani

4:30 PM

An FPGA-based Brain Computer Interfacing using Compressive Sensing and Machine Learning

Ritu Ranjan Shrivastwa, Vikramkumar Pudi, Anupam Chattopadhyay

4:50 PM

Enabling efficient fine-grained DRAM activations with interleaved I/O

Chao Zhang, Xiaochen Guo

5:10 PM

Ferroelectric Transistors for Neuromorphic Computing

Asif Islam Khan

5:30 PM

Nonvolatile memory and computing using emerging ferroelectric transistors

Xueqing Li, Longqiang Lai

5:50 PM

Collective computing using phase transition based dynamical systems

Nikhil Shukla, Suman Datta, Arijit Raychowdhury

5:10 PM

Software Support for Heterogeneous Computing

Siqi Wang, Alok Prakash, Tulika Mitra

5:30 PM

Predictive Modeling for CPU, GPU, and FPGA Performance and Power Consumption: A Survey

Kenneth O'Neal, Philip Brisk