Keynote 1: Rethinking Computer Architecture Design in the Era of Large Language Models

Chair: Himanshu Thapliyal

 
Abstract: The rapid advancement of large language models (LLMs) has revolutionized various fields, from natural language processing to artificial intelligence-driven applications. However, the unprecedented scale and complexity of these models demand a fundamental reexamination of traditional computer architecture design. In this keynote, we will explore the impact of LLMs on hardware and software architectures, addressing the unique challenges and opportunities they present. We will delve into innovative approaches to memory management, parallel processing, and energy efficiency tailored to the needs of LLMs. By integrating insights from cutting-edge research and industry practices, this keynote aims to chart a path forward for creating optimized, scalable, and sustainable computing systems capable of harnessing the full potential of large language models.

Bio:As a leader in AI computing, Yiran Chen is the John Cocke Distinguished Professor of Electrical and Computer Engineering at Duke University. He serves as the principal investigator and director of the NSF AI Institute for Edge Computing – Athena, the NSF Industry-University Cooperative Research Center for Alternative Sustainable and Intelligent Computing (ASIC), and the co-director of the Duke Center for Computational Evolutionary Intelligence (DCEI). Dr. Chen is the author of over 600 publications and holds 96 US patents. His contributions have been recognized with numerous awards and honors, including the IEEE Circuits and Systems Society's Charles A. Desoer Technical Achievement Award and the IEEE Computer Society's Edward J. McCluskey Technical Achievement Award. He is a Fellow of the AAAS, ACM, IEEE, and NAI, and currently serves as the chair of ACM SIGDA and the inaugural Editor-in-Chief of IEEE Transactions on Circuits and Systems for Artificial Intelligence (TCASAI). He is also a founding member of the Academic Alliance on AI Policy (AAAIP).

Keynote 2: Emerging Technologies for the Era of Pervasive Intelligence

Chair: Garrett Rose

 
Abstract: The talk will address the new era of pervasive intelligence, driven by ubiquitous AI, silicon proliferation, and software driven systems. It then covers the key emerging technologies such as AI-driven design automation, heterogeneous systems, digital twining, next generation of computing architectures, etc that fuel the massive digital transformation towards the pervasive intelligence. The speaker will also share what we can do to stay at the forefront of these innovation.

Bio: Brandon Wang is a Vice President, VP of Technology Strategy at Office of the CEO at Synopsys. Brandon oversees corporate level technology roadmaps and strategies for growth, including global strategic and ecosystem partnerships, and M&A/investments for new horizons. He also heads the Chief Innovation Office, championing organic innovations and worldwide academic and research partnerships. Prior to joining Synopsys in 2018, Brandon served executive and senior roles at Cadence, ARM, Qualcomm, and Lattice in chief strategy office, product marketing, and R&D organizations for over two decades. Brandon is currently serving at the board of Efabless corporation, and as a limited partner/Investment Council member to Imec.Xpand, an affiliated VC to Imec. He is also a Limited Partner to AIX, a leading venture capital firm focusing on AI investment. An Electrical and Computer Engineer by training, Brandon holds 10 patents, and has published at 20+ IEEE conferences, in journal papers and invited talks in the areas of 3D-IC, Machine Learning, HW security, High-speed Interfaces, Low Power CPU, FPGA and Memory Designs. He also has an MBA degree from the Wharton School at the University of Pennsylvania.

Keynote 3: Pushing Quantum Computers Beyond Classical Simulation

Chair: Himanshu Thapliyal

 
Abstract: Trapped ion quantum computers have many excellent properties for enabling both fault-tolerant quantum computation and algorithms run directly on the physical qubit layer. Demonstrating quantum circuits that are difficult to classically solve is a necessary condition for providing computational value with quantum computers, and in this talk we will discuss how the classical simulation complexity of quantum circuits scales under various assumptions. Pushing beyond minimum demonstrations on the physical layer, large scale applications require fault-tolerance and the demonstration of quantum error correcting codes. I will end with a discussion about how quantum computers are now at the point of moving long theorized error correction protocols into experimental realization.

Bio: Dr. Russell Stutz is currently leading the Commercial Hardware group of Quantinuum, where he is responsible for the design and build of commercial quantum computers. He received his Bachelor of Science in Physics from the University of Kansas performing research in experimental particle physics. Upon graduation he received a commission in the US Air Force. As an Air Force officer, he worked on laser research at the Air Force Research Lab, Directed Energy Directorate at Kirtland AFB, NM. Dr. Stutz received his PhD from the University of Colorado-Boulder in atomic, molecular, and optical physics in 2010 studying the electron electric dipole moment in trapped molecular ions. After receiving his PhD, Dr. Stutz worked industrial research and development at AOSense developing quantum sensors, as well as Lockheed Martin. He started at Honeywell Quantum Solutions, a precursor of Quantinuum, in 2016.

Keynote 4: Precision Agriculture and VLSI

Chair: Juergen Becker

 
Abstract: Precision agriculture and environmental monitoring present important use cases for semiconductors. However, meeting the unique challenges of these applications will require innovations in packaging and system architecture. This talk will discuss the requirements of precision agriculture and environmental marketing, some of the technological challenges that must be addressed, and possible approaches.

Bio: Marilyn Wolf is Elmer E. Koch Professor of Engineering and Director of ORED Engineering and Technology Initiatives at the University of Nebraska Lincoln. She received her BS, MS, and PhD in electrical engineering from Stanford University in 1980, 1981, and 1984, respectively. She was with AT&T Bell Laboratories from 1984 to 1989. She was on the faculty of Princeton University from 1989 to 2007 and was Farmer Distinguished Chair at Georgia Tech from 2007 to 2019. Her research interests included embedded computing, embedded video and computer vision, and VLSI systems. She has received the IEEE Kirchmayer Graduate Teaching Award, the IEEE Computer Society Goode Memorial Award, the ASEE Terman Award, IEEE Circuits and Systems Society Education Award, and the ACM SIGDA Distinguished Service Award. She is a Fellow of the IEEE and ACM and an IEEE Computer Society Golden Core member.

Keynote 5: Hardware Security 2.0 (and the Unmistakable Role of Generative AI)

Chair: Himanshu Thapliyal

 
Abstract: With the emergence of the Internet of Things (IoT) regime that promises exciting new applications from smart cities to connected autonomous vehicles, security of edge devices has come to the forefront of the system design process. Recent discoveries and reports on numerous security attacks on microchips and circuits violate the well-regarded concept of hardware trust anchors. Current business model and the supply chain eco-system for microelectronics give rise to unprecedented security issues and accentuate the need for secure, trustworthy hardware. It has prompted system designers to develop novel security primitives, design-for-security, and test/validation solutions to achieve secure hardware for diverse IoT applications. Emerging security issues and countermeasures have also led to interesting interplay between security and verification. Verification of hardware for security and trust has become an integral part of the system design flow. The talk will cover spectrum of challenges associated with hardware security and describe emerging solutions in creating secure trustworthy hardware that can enable IoT security for the mass. It will outline the need and challenges for verification of an electronic design’s security properties and the motivation for learning-guided security design and verification. Finally, it will outline how AI-driven assurance of hardware, specifically the usage of generative AI, is creating a promising new paradigm of hardware-centric IoT security.

Bio: Dr. Swarup Bhunia is currently a preeminence professor of cybersecurity and Semmoto Endowed Professor of Internet of Things (IoT) at University of Florida. He serves as the Director of the Warren B. Nelms Institute for the Connected World. Earlier, he was appointed as the T. and A. Schroeder associate professor of Electrical Engineering and Computer Science at Case Western Reserve University. He has over twenty years of research and development experience with 10 authored/edited books and over 300 publications in peer-reviewed journals and premier conferences and ten authored/edited books. His research interests include hardware security and trust, adaptive nanocomputing and novel test methodologies. Dr. Bhunia received IBM Faculty Award, National Science Foundation career development award, Semiconductor Research Corporation Inventor Recognition Award, IEEE HOST Hall of Fame award, University of Florida Research Foundation Professorship Award, SRC technical excellence award as a team member, and several best paper awards/nominations. He is co-founding editor-in-chief of a Springer journal on hardware and systems security. Dr. Bhunia received his PhD from Purdue University on energy-efficient and robust electronics. He is a Fellow of the IEEE.

Keynote 6: Some Trends in SoC Power Optimization

Chair: Juergen Becker

 
Abstract: The always increasing transistor count in modern systems on chip, as well the exploding number of devices connected to the internet of things, is demanding new design approaches. One fundamental issue and challenge is the design optimization, mainly power optimization. In some applications, as implantable devices, reliability and power optimization is fundamental. It will be done a short overview of some techniques for power optimization at different levels of abstraction. But a focus will be related to the physical design optimization, as it is becoming a more and more important issue, not only for power optimization, but also for connections and vias optimization, increasing routability as well reliability. It will be shown some techniques and examples of optimization at architectural and physical design level.

Bio: Ricardo Reis received a Bachelor degree in Electrical Engineering from Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil, in 1978, and a Ph.D. degree in Microelectronics from the National Polytechnic Institute of Grenoble (INPG), France, in 1983. Doctor Honoris Causa by the University of Montpellier in 2016. He is a full professor at the Informatics Institute of Federal University of Rio Grande do Sul. His main research includes physical design automation, design methodologies, fault tolerant systems and microelectronics education. He has more than 700 publications including books, journals and conference proceedings. He was vice-president of IFIP (International Federation for Information Processing) and he was also president of the Brazilian Computer Society (two terms) and vice-president of the Brazilian Microelectronics Society. He is an active member of CASS and he received the 2015 IEEE CASS Meritorious Service Award. He was vice-president of CASS for two terms (2008/2011), as well CASS BoG member for two terms. He is the founder of the Rio Grande do Sul CASS Chapter, which got the World CASS Chapter of The Year Award 2011, 2012, 2018 and 2022, and R9 Chapter of The Year 2013, 2014, 2016, 2017 and 2020. He is a founder of several conferences like SBCCI and LASCAS, the CASS Flagship Conference in Region 9. He was the General or Program Chair of several conferences like IEEE ISVLSI, SBCCI, IFIP VLSI-SoC, ICECS, PATMOS. Ricardo was the Chair of the IFIP/IEEE VLSI-SoC Steering Committee, vice-chair of the IFIP WG10.5 and he is Chair of IFIP TC10. he received the Researcher of the Year Award in the state of Rio Grande do Sul. He is a founding member of the SBC (Brazilian Computer Society) and also founding member of SBMicro (Brazilian Microelectronics Society). He was member of CASS DLP Program (2014/2015), and he has done more than 70 invited talks in conferences. He is the CASS representative at the IEEE IoT Technical Committee. Ricardo received the IFIP Fellow Award in 2021 and the ACM/ISPD Lifetime Achievement Award in 2022. He received the 2023 IEEE CASS John Choma Educational Award and the 2024 Best Associate Editor of IEEE CASS Magazine.

Poster Session 1

Poster Session 2