Sung-Mo Steve Kang

University of California, Santa Cruz

65 Years of Integrated Circuit Innovations – From a Single Transistor to Trillions of Transistors on Chip

Omar Paranaiba

Federal University of Minas Gerais, Brazil

Unconventional Computing with Unconventional Nanotechnologies

Jürgen Becker

Karlsruhe Institute of Technology – KIT, Germany

Smart Scalable & Embedded Automotive Supercomputing

Patrick Groeneveld

Cerebras Systems, USA

A fresh perspective on Moore’s Law

Paul Franzon

Department of Electrical and Computer Engineering North Carolina State University, USA

Chiplets for AI – AI for chiplets

Melanie Berg

Founder/CEO of Space R3 LLC, USA

Fault Tolerance Assurance for Safety-Critical Automotive and Space Applications

Sung-Mo Steve Kang - University of California, Santa Cruz

65 Years of Integrated Circuit Innovations – From a Single Transistor to Trillions of Transistors on Chip

Abstract:
The year 2023 marks the 65th anniversary of Integrated circuit invention. Jack Kilby invented the first integrated circuit 65 years ago, following the invention of a transistor about a decade prior. Today the chip technology is recognized as the most critical technology in the world. During the last half century, the semiconductor chip industry has made phenomenal progresses to benefit our daily life. To mention some, 5G mobile communication from anywhere to everywhere, virtual meetings and remote learning under the pandemic, autonomous cars, energy-efficient lighting, and AI applications as in ChatGPT and health care. An average-car of today contains 1200 chips. Shortage of less-than-a-dollar chips forced the manufacturing line of high-price cars to stop and be idle. Fifty years ago, the most advanced Intel microprocessor chip used a few thousand transistors. At present, the most advanced wafer-scale AI chip contains more than two trillion transistors. This phenomenal advancement, riding on the wave of Moore’s Law and Beyond, owes a great deal to innovations in materials, devices, circuits and systems, EDA technology, manufacturing, and packaging. In this talk, we will highlight and discuss benchmarking innovations in CMOS and heterogeneous VLSI circuits, systems, and applications. In view of manufacturability, energy efficiency and reliability of VLSI system chips, the figure-of-merit of VLSI chips can be pitched as “the smaller, the cooler, the better.” Emergent technologies, including memristor technology, will be discussed along with their applications for ultra-dense low-power intelligent VLSI systems, future neuromorphic computing, and generative AI and scientific hardware acceleration.

Short Bio:
Sung-Mo Steve Kang is a Distinguished Chair Professor Emeritus and Distinguished Research Professor at the Baskin School of Engineering, UC Santa Cruz. He is Chancellor Emeritus of UC Merced and President Emeritus of KAIST. He has published over five hundred journal and conference papers, sixteen patents, and over ten books including a textbook on CMOS digital IC analysis and design, which has been translated into multiple languages and used globally. Before returning to academia in 1985, he led the development of world’s premier fully-CMOS 32-bit VLSI microprocessor chipsets for telecommunication and computing applications as a technical supervisor of AT&T Bell laboratories, Murray Hill, New Jersey. He has received honors including the Silicon Valley Engineering Hall of Fame Induction, Alexander von Humboldt Senior US Scientists Award, IEEE Millennium Medal, IEEE Circuits and Systems (CAS) Society Mac Van Valkenburg Award, IEEE CAS Society Charles A. Desoer Technical Excellence Award, US Semiconductor Research Corporation (SRC) Technical Excellence Award, IEEE Leon K. Kirchmayer Graduate Teaching Technical Field Award, IEEE CAS Society John Choma, Jr. Education Award, and Chang-Lin Tien Education Leadership Award. He received his B.S. degree from Fairleigh Dickinson University, Teaneck, New Jersey in 1970, honorary B.S degree from Yonsei University, M.S. degree from the State University of New York at Buffalo in 1972, and Ph.D. degree from the University of California at Berkeley in 1975. Dr. Kang is a Life Fellow of the IEEE, a Fellow of the Association for Computing Machinery (ACM) and the American Association for the Advancement of Science (AAAS), a Life Member of the Korean Academy of Science and Technology, and a Foreign Member of the National Academy of Engineering, Korea. His current research interest includes neuromorphic computing, low-power VLSI circuits and systems, and emerging technologies for heterogeneous systems integration.

Omar Paranaiba - Federal University of Minas Gerais, Brazil

Unconventional Computing with Unconventional Nanotechnologies

Abstract:
Many scientists state that Moore's Law is close to its end. One of the main reasons is the physical limit of silicon transistors' miniaturization. No prominent successor technology to the current CMOS logic exists, but some possible alternatives have been investigated. In this talk, we will discuss the historical evolution of computer machines until the end of the golden era, when designers could develop software, architecture, implementation, and devices independently. So, a question comes to mind: What will we have in the future? Do we need to continue controlling the electric current to perform computation? Are there other alternatives? A wide variety of new nanotechnologies will generate many possibilities for developing new computational applications at low energy, high speed, and high resilience. Let's see some of these possible alternatives.

Short Bio:
Omar Paranaiba Vilela Neto received his undergrad degree in Computer Engineering (2003), M.Sc. degree (2006), and Ph.D. degree (2009) in Electrical Engineering from PUC-Rio, Brazil. Since 2010, he is a Professor at the Department of Computer Science, Federal University of Minas Gerais (UFMG), Brazil. His main research interests involve emerging nanotechnologies, nanocomputing and computational nanotechnology. Omar is head of the Nanocomputing and Computational Nanotechnology Laboratory (NanoComp) at the UFMG. Omar is a member IEEE, Brazilian Computer Society (SBC), and Brazilian Microelectronics Society (SBMicro). He is an Associate Researcher of the Brazilian National Research Council (CNPq) and author and co-author of more than 100 publications in scientific journals and conferences.

Jürgen Becker - Karlsruhe Institute of Technology – KIT, Germany

Smart Scalable & Embedded Automotive Supercomputing

Abstract:
The emerging field of reliable embedded electronic High-Performance Computing (HPC) systems, incl. heterogenous multi-core (MC), accelerator artificial intelligence (AI) and cyber-physical systems (CPS) integration, is essential and challenging for actual and future silicon technologies. Here, on one side increasing monolythic integration of cooperating computational and physical sensor components is necessary, e. g. in embedded and smart on-demand automatized environments as diverse as applied in space, avionics, automotive, chemical processes, civil infrastructure, energy, healthcare, manufacturing (Industry 4.0), transportation, entertainment, and communication/consumer appliances. Moreover, future complex dynamically adaptive and multi-domain electronic system integration tends to be more and more dependent on distributed real-time and embedded HPC availability. This results in the strong demand of newly operating decentralized/centralized intelligent, interconnected, and silicon technology integrated solutions, subject to increased performance needs to facilitate computationally intensive algorithms, power consumption to be minimized, as well as sufficient degrees of reliability and verifiability to employ digital systems in safety-critical environments, e. g. especially also in future automotive system integration. Existing technology must evolve in order to meet such scalable and high requirements, whereas open source hardware and AI could also play key roles in this process. Multipurpose adaptivity, connectivity and reliability are crucial, especially in scaling down silicon technologies according to Moore for future processor technologies incl. dynamically reconfigurable and AI accelerators. This requires in addition new approaches for parallel programming, reference technology platforms (RTP) and standardized tool flows. The talk will discuss challenges of high-end heterogenous multi-core/accelerator HPC platforms incl. their reliable SoC and SiP hardware/software integration, e. g. towards smart, scalable & embedded Automotive Supercomputing solutions. This includes several automotive related project initiatives like ARAMiS (Automotive, Railway and Avionics Multicore Systems - https://www.aramis2.com ), EPI (European Processor Initiative - https://www.european-processor-initiative.eu ), XANDAR (Safety and Security for Embedded Software Systems - https://xandar-project.eu ), as well as the new national project CeCaS (CentralCarServer - https://www.infineon.com/cms/en/about-infineon/press/press-releases/2023/INFXX202302-070.html), among others.

Short Bio:
Jürgen Becker received the Diploma and Ph.D. (Dr.-Ing.) degree from Technical University Kaiserslautern, Germany. Since 2001 he is full professor for embedded electronic systems and Head of the Institute for Information Processing Technologies (ITIV) at the Karlsruhe Institute of Technology (KIT). From 2005-2009 he has been appointed as Vice President for Education at Universitaet Karlsruhe (TH) and Chief Higher Education Officer (CHEO) at KIT from 2009-2012. Since 2012 till 2014 he served as Secretary General of CLUSTER, an association of 12 leading Technical Universities in Europe. His research interests include Hardware/Software System-on-Chip (SoC) Integration, Cyber-Physical Systems (CPS), Heterogenous Multicore (MC) Architectures and Design Methods, Reconfigurable Computing, with application in Embedded Systems (Automotive, Industry 4.0, Avionics, HPC Scientific Applications incl. Physics Detector Experiments). He authored over 500 papers in peer-reviewed international journals and conferences, incl. 30 patents and has been coordinating several national and european projects. Prof. Becker is active in numerous international conferences, as Chairman in TPC & Steering Committees, e. g. IEEE ISVLSI, IEEE SOCC, RAW, FPL, PATMOS, IFIP VLSI-SoC, DATE, SBCCI, ARC, FCCM, FPT, among others.

Patrick Groeneveld - Cerebras Systems, USA

A fresh perspective on Moore’s Law

Abstract:
The Jevons paradox, a phenomenon first described by a 19th-century British economist, refers to the counterintuitive observation that technological improvements in efficiency can actually lead to increased - rather than reduced - resource consumption. In the case of mobile electronics, we can see this paradox at work, as the gains from Moore's law scaling are almost exclusively reinvested into additional features rather than energy savings. For instance, modern smartphones contain SoCs with 20 times more transistors than a decade ago. Currently the phone in our pocket may contain almost as many transistors as there are grains of sand on earth (!). But the power consumption has remained flat while improvements in functionality have been relatively modest. Another recent example can be seen in the significant energy required to power machine learning hardware, the increase of which far outstrips the rate of regular compute efficiency. Jevons paradox also applies to adjacent domains. While automotive propulsion has become more efficient, the gains are largely negated by the fact that cars have been growing into tall SUVs with oversized wheels that serve only aesthetic purposes. In this keynote presentation, we will discuss the scale of this paradox in microelectronics and in electrical systems more generally.

Short Bio:
Patrick Groeneveld currently focuses on machine learning hardware synthesis. At Cerebras Systems, a AI hardware startup, that hardware is the world's first monolithic supercomputer with 2.4 Trillion transistors. Patrick spent many years working in the EDA industry. During his tenure as Chief Technologist at Magma Design Automation, he was a part of the team that developed a groundbreaking RTL-to-GDS2 synthesis product. Additionally, Patrick served as a Full Professor of Electrical Engineering at Eindhoven University. Currently, he teaches a class in the EE department at Stanford University and also serves as the finance chair on the Executive Committee of the Design Automation Conference. Patrick received his MSc and PhD degrees from Delft University of Technology in the Netherlands.

Paul Franzon - Department of Electrical and Computer Engineering North Carolina State University, USA

Chiplets for AI – AI for chiplets

Abstract:
Modern machine learning workloads are increasing in scale at a rapid rate. For example, GPT-3 has 175 billion parameters, requiring 570 GB of storage, and benefits from having high-bandwidth interfaces between the logic and the storage. We describe a chiplet based solution and a 3D logic on memory based solution to this problem. The chiplet based solution relies on a scalable RISC-V core and accelerator pair, one accelerator for sparse CNN layers, and another for MLP and LSTM acceleration. The chiplet set was recently demonstrated in 55 nm CMOS. The 3D logic on memory solution leverages high density hybrid bonding and TSVs, together with the SIMD processor array and was designed to handle a wide variety of machine learning workloads. This solution can handle peak bandwidths of 130 Tbps and outperforms all other solutions in area efficiency, and all other programmable solutions in power efficiency. It is currently being redesigned for emerging workloads and arrange a memory solution. Hybrid bonding also enables radical improvements in PPA for two chip stacks and enables design obfuscation of design intent. Recent experiments demonstrating these solutions will be discussed. Chiplet based design comes with a lot of complexity, in that there are a lot of factors to consider while trying to determine an optimal design set. We have been exploring generative ML methods to drive chiplet early design and will discuss some results to date. Generative ML has potential to excel at multifactor optimization and to manage complex design steps. One challenge in generative ML is how to achieve potential with reasonable training time. Potential solutions to this problem will be discussed.

Short Bio:
Paul D. Franzon is currently the Cirrus Logic Distinguished Professor and the Director of Graduate programs in the Department of Electrical and Computer Engineering at North Carolina State University. He earned his Ph.D. from the University of Adelaide, Adelaide, Australia. He has also worked at AT&T Bell Laboratories, DSTO Australia, Australia Telecom, Rambus, and four companies he cofounded, Communica, LightSpin Technologies, Polymer Braille Inc. and Indago Technologies. His current interests include applying machine learning to EDA, building AI accelerators, RFID, advanced packaging, 2.5D and 3DICs and secure chip design. He has lead several major efforts and published over 300 papers in these areas. In 1993 he received an NSF Young Investigators Award, in 2001 was selected to join the NCSU Academy of Outstanding Teachers, in 2003, selected as a Distinguished Undergraduate Alumni Professor, received the Alcoa Research Award in 2005, the Board of Governors Teaching Award in 2014, and the Distinguished Graduate Alumni Professor in 2021. He has been awarded faculty awards from Qualcomm, IBM and Google. He served with the Australian Army Reserve for 13 years as an Infantry Soldier and Officer. He is a Fellow of the IEEE.

Melanie Berg - Founder/CEO of Space R3 LLC, USA

Fault Tolerance Assurance for Safety-Critical Automotive and Space Applications

Abstract:
Safety-critical applications must adhere to stringent reliability and availability requirements. It has been shown that ionizing particles can cause faults in microelectronics that inhibit operation and hence reduce reliability. Consequently, fault tolerant schemes have been developed to sustain system functionality at its required level. When implementing fault tolerance, additional hardware (logic) is needed. The increase in hardware can have a significant impact on a system’s size, weight, and power (SWAP); and can compromise system integration. To reduce SWAP, fault tolerance is strategically inserted into portions of a system, deemed to be the most critical. As a result, residual risk exists, and requires probabilistic error rates to be calculated. In this talk, types of ionization and their effects on microelectronics (terrestrially and in space) will be explained. Methods of fault tolerance assurance, from testing to probabilistic fault prediction, will be discussed as they pertain to safety-critical applications in the automotive and space industries.

Short Bio:
Mrs. Melanie Berg has over 30-years of experience as a designer, verification engineer, instructor, and reviewer for ASIC and FPGA applications. Her more visible accomplishments are her contributions to the FPGA designs for the NASA sponsored New Horizons Pluto and Beyond Mission; and her research/development in mitigation strategies. Melanie is a member of the Radiation Effects and Analysis group at NASA/GSFC; and is the founder/CEO of Space R3 LLC. She has published and presented several papers regarding: ionization and microelectronic error-response characterization, reliable synchronous design methodology, robust verification techniques, mitigation strategies for critical circuitry, reliability/survivability prediction calculations, and hardness assurance for space flight systems.