ISVLSI 2023

Tuesday June 20, Room Vivace 1
Start time	Title	Speaker
14:00	ISVLSI2023 introduction
14:10	Embedded Tutorial - Using Virtual Boards to Teach Digital Circuit Design	Andre Reis (UFRGS, Brazil) More details: click here!
15:10	Coffee Break
15:30	Industrial Panel: Microelectronics Challenges in Latin America
17:00	Session 1: VLSI for Applied and Future Computing - part I	Chair: André Reis (UFRGS, Brazil)
17:00	A Digital SRAM Computing-in-Memory Design Utilizing Activation Unstructured Sparsity for High-Efficient DNN Inference	Baiqing Zhong, Mingyu Wang, Chuanghao Zhang, Yangzhan Mai, Xiaojie Li and Zhiyi Yu
17:20	Evaluation of Digital Circuit Design by Combining Two- and Multi-Level Approximate Logic Synthesis	Gabriel Ammes, Paulo Butzen, Andre Reis and Renato Ribas
17:40	tubGEMM: Energy-Efficient and Sparsity-Effective Temporal-Unary-Binary Based Matrix Multiply Unit	Prabhu Vellaisamy, Harideep Nair, Joseph Finn, Manav Trivedi, Albert Chen, Anna Li, Tsung-Han Lin, Perry Wang, Shawn Blanton and John Paul Shen
18:10	Opening Session
20:00	Welcome Reception Music with 3Nós Acústico @3nos.acustico (20h - 22h)

Wednesday June 21, , Room Vivace 1
Start time	Title	Speaker
08:30	Session 2: Emerging and Post-CMOS Technologies	Chair: Mounir Boukadoum (Univ. Quebec at Montreal, Canada)
08:30	Signal Distribution Networks for Scalable Placement and Routing of Field-coupled Nanocomputing Technologies	Marcel Walter, Benjamin Hien and Robert Wille Versatile
08:50	Photonic Convolution Engine based on Phase-Change Materials and Stochastic Computing	Raphael Cardoso, Clément Zrounba, Mohab Abdalla, Paul Jimenez, Mauricio Gomes de Queiroz, Benoit Charbonnier, Fabio Pavanello, Ian O'Connor and Sebastien Le Beux
09:10	Robustness and Power Efficiency in Spin-Orbit Torque-Based Probabilistic Logic Circuits	Kamal Danouchi, Guillaume Prenat, Philippe Talatchian, Louis Hutin and Lorena Anghel
09:20	A Compact Ferroelectric 2T-(n+1)C Cell to Implement AND-OR Logic in Memory	Yi Xiao, Yixin Xu, Shan Deng, Zijian Zhao, Sumitha George, Kai Ni and Vijaykrishnan Narayanan
09:40	Coffee-break
10:10	Session 3: VLSI for Applied and Future Computing - part II	Chair: Raafat Lababidi (Ensta, Bretagne, France)
10:30	Federated Learning with Spiking Neural Networks in Heterogeneous Systems	Sadia Anjum Tumpa, Sonali Singh, Md Fahim Faysal Khan, Mahmut Taylan Kandemir, Vijaykrishnan Narayanan and Chita R. Das
10:50	Fe-GCN: A 3D FeFET Memory Based PIM Accelerator for Graph Convolutional Networks	Hongtao Zhong, Yu Zhu, Longfei Luo, Taixin Li, Chen Wang, Yixin Xu, Tianyi Wang, Yao Yu, Vijaykrishnan Narayanan, Yongpan Liu, Liang Shi, Huazhong Yang and Xueqing Li
11:10	Design Exploration of Dynamic Multi-Level Ternary Content-Addressable Memory Using Nanoelectromechanical Relays	Taixin Li, Hongtao Zhong, Sumitha George, Vijaykrishnan Narayanan, Liang Shi, Huazhong Yang and Xueqing Li
11:30	65 Years of Integrated Circuit Innovations – From a Single Transistor to Trillions of Transistors on Chip	Keynote: Sung-Mo Steve Kang (University of California at Santa Cruz, USA)
12:30	Lunch
14:00	Unconventional Computing with Unconventional Nanotechnologies	Keynote Omar Paranaiba (Federal University of Minas Gerais, Brazil)
15:00	Special Session 1: Secure and Dependable Cyber-Physical Systems	Chair: Achim Rettberg (Carl von Ossietzky Universität Oldenburg, Germany)
15:00	iTPM: Exploring PUF-based Keyless TPM for Security-by-Design of Smart Electronics	Venkata Karthik Vishnu Vardhan Bathalapalli, Saraju Mohanty, Elias Kougianos, Vasanth Iyer and Bibhudutta Rout
15:20	2.0: Machine Learning based Monitoring and Authentication of PUF-Integrated Secure Edge Data Center	Seema Aarella, Saraju Mohanty, Elias Kougianos and Deepak Puthal Fortified-Edge
15:40	Coffee break
16:10	Revolutionizing Cyber Security: Exploring the Synergy of Machine Learning and Logical Reasoning for Cyber Threats and Mitigation	Deepak Puthal, Saraju Mohanty, Amit Kumar Mishra, Chan Yeob Yeun and Ernesto Damiani
16:30	IoMT Synthetic Cardiac Arrest Dataset for eHealth with AI-based Validation	Joy Dutta and Deepak Puthal
16:50	UNIC-CAS Program and IEEE CASS opportunities	Manuel Delgado-Restituto (US-CSIC, Sevilha, Spain)
18:00	Social Event at the Landmark of the Three Borders Buses depart from the lobby at the hotel at 18:00h. At Landmark of the Three Borders there will be dinner and drinks, music and folklore dance show. Buses will return from Landmark of the Three Borders at 22:30h, we will arrive at hotel around 23:10h.

Thursday June 22, , Room Vivace 1
Start time	Title	Speaker
08:30	Session 4: Circuits, Reliability, and Fault-Tolerance	Chair: Victor Grimblatt (Synopsys, Chile)
08:30	Formal Temporal Characterization of Register Vulnerability in Digital Blocks	Damiano Zuccala, Katell Morin-Allory, Jean-Marc Daveau and Philippe Roche
08:50	Harnessing the Effects of Process Variability to Mitigate Aging in Cloud Servers	Arthur Lorenzon, Guilherme Korol, Marcelo Brandalero and Antonio Carlos Schneider Beck Filho
09:10	Evaluating an XOR-based Hybrid Fault Tolerance Technique to Detect Faults in GPU Pipelines	Giani Augusto Braga, Jose Rodrigo Azambuja and Marcio M. Goncalves
09:30	Modeling and Analysis of Switched-Capacitor Converters as a Multi-port Network for Covert Communication	Yerzhan Mustafa and Selcuk Kose
09:50	Using Lyapunov Exponents and Entropy to Estimate Sensitivity to Process Variability	Elias de Almeida Ramos and Ricardo Reis
10:10	Coffee Break
10:30	A fresh perspective on Moore’s Law	Keynote: Patrick Groeneveld (Cerebras Systems, USA) Moderator: Juergen Becker (KIT, Germany)
12:30	Lunch
14:00	Smart Scalable & Embedded Automotive Supercomputing	Keynote: Jürgen Becker (Karlsruhe Institute of Technology – KIT, Germany) Moderator: Jose Rodrigo Azambuja (UFRGS, Brazil)
15:00	Session 5: Digital Circuits and FPGA based Designs - part I	Chair: Jose Rodrigo Azambuja (UFRGS, Brazil)
15:00	Dynamic Offloading Decisions for Improved Performance and Energy Efficiency in Heterogeneous IoT-Edge-Cloud Continuum	Julio Costella Vicenzi, Guilherme Korol, Michael Guilherme Jordan, Wagner Ourique de Morais, Hazem Ali, Edison Pignaton de Freitas, Mateus Beck Rutzig and Antonio Carlos Schneider Beck Filho
15:20	Resource Provisioning for CPU-FPGA Environments with Adaptive HLS-Versioning and DVFS	Michael Jordan, Guilherme Korol, Tiago Knorst, Mateus Rutzig and Antonio Carlos Schneider Beck Filho
15:40	Design Space Exploration for CNN Offloading to FPGAs at the Edge	Guilherme Korol, Michael Jordan, Mateus Rutzig, Jeronimo Castrillon and Antonio Carlos Schneider Beck Filho
16:00	Machine Learning and Polynomial Chaos models for Accurate Prediction of SET Pulse Current	Vishu Saxena, Yash Jain and Sparsh Mittal
16:20	Poster Session and coffee-break
17:00	Session 6: Digital Circuits and FPGA based Designs - part II	Chair: Antonio Carlos Beck Filho (UFRGS, Brazil)
17:00	A 3 TOPS/W RISC-V Parallel Cluster for Inference of Fine-Grain Mixed-Precision Quantized Neural Networks	Alessandro Nadalini, Georg Rutishauser, Alessio Burrello, Nazareno Bruschi, Angelo Garofalo, Luca Benini, Francesco Conti and Davide Rossi
17:20	CWAHA: Cluster-Wise Approximation for Hardware implementation of Arithmetic functions	Omkar Ratnaparkhi and Madhav Rao
17:40	Column-Weighted Probabilistic GDBF Decoder for Irregular LDPC Codes	Changfu He, Keyue Deng, Suwen Song and Zhongfeng Wang
18:00	Reverse Engineering of RTL Controllers from Look-Up Table Netlists	Sundarakumar Muthukumaran, Aparajithan Nathamuni Venkatesan, Kishore Pula, Ram Venkat Narayanan, Ranga Vemuri and John Emmert
18:20	Performance Optimized Clock Tree Embedding for Auto-Generated FPGAs	Grant Brown, Ganesh Gore and Pierre-Emmanuel Gaillardon
18:40	An FPGA-Based Reconfigurable CNN Training Accelerator Based on Decomposable Winograd	Hui Wang, Jinming Lu, Jun Lin and Zhongfeng Wang
20:30	Gala Dinner at Bardana Grill in the Hotel Recanto Cataratas Services of food and drinks from 20:30h to 22:30h Music Renato Costa @fumeguitar (20:30-23:30h)

Friday June 23, , Room Vivace 1
Start time	Title	Speaker
08:30	Session 7: System Design and Security - Part I	Chair: Paulo F. Butzen (UFRGS, Brazil)
08:30	DREAM: Distributed Reinforcement Learning Enabled Adaptive Mixed-Critical NoC	Nidhi Anantharajaiah, Yunhe Xu, Fabian Lesniak, Tanja Harbaum and Juergen Becker
08:50	Power, Performance and Reliability Evaluation of Multi-thread Machine Learning Inference Models Executing in Multicore Edge Devices	Geancarlo Abich, Anderson Ignacio da Silva, José Eduardo Thums, Rafael da Silva, Altamiro Amadeu Susin, Ricardo Reis and Luciano Ost Power,
09:10	A Secure Design Methodology to Prevent Targeted Trojan Insertion during Fabrication	Arjun Suresh, Siva Nishok Dhanuskodi and Daniel Holcomb
09:30	Application Profiling Using Register-Instruction Hardware Performance Counters	Anand Menon, Amisha Srivastava, Shamik Kundu and Kanad Basu
09:50	Coffee Break
10:20	Session 8: System Design and Security - part II	Chair: José Augusto Nacif (UFV, Brazil)
10:20	Benchmarking of SoC-level Hardware Vulnerabilities: A Complete Walkthrough	Shams Tarek, Hasan Al Shaikh, Sree Ranjani Rajendran and Farimah Farahmandi
10:40	Revisiting Trojan Insertion Techniques for Post-Silicon Trojan Detection Evaluation	Vedika Saravanan, Mohammad Walid Charrwi and Samah Mohamed Saeed
11:00	Design and Evaluation of M-Term Non-Homogeneous Hybrid Karatsuba Polynomial Multiplier	Sanampudi Gopala Krishna Reddy, Gogireddy Ravi Kiran Reddy, Vasanthi D R and Madhav Rao
11:20	LAT-UP: Exposing Layout-Level Analog Hardware Trojans Using Contactless Optical Probing	Sajjad Parvin, Mehran Goli, Thilo Krachenfels, Shahin Tajik, Jean-Pierre Seifert, Frank Sill Torres and Rolf Drechsler
11:40	Fault Tolerance Assurance for Safety-Critical Automotive and Space Application	Keynote: Melanie Berg (Space R3 LLC, USA) Moderator: Fernanda Lima Kastensmit (UFRGS, Brazil)
12:40	Lunch
14:00	Chiplets for AI – AI for chiplets	Keynote: Paul Franzon (North Carolina State University, USA) Moderator: Fernanda Lima Kastensmit (UFRGS, Brazil)
15:00	Session 9: Computer-Aided Design and Verification	Chair: Geancarlo Abich (Brazil)
15:00	Machine Learning Techniques for Pre-CTS Identification of Timing Critical Flip-Flops	Chunkai Fu, Ben Trombley, Hua Xiang, Gi-Joon Nam and Jiang Hu
15:20	LEX - A Cell Switching Arcs Extractor: A Simple SPICE-Input Interface for Electrical Characterization	Rodrigo Wuerdig, Vitor Maciel, Ricardo Reis and Sergio Bampi
15:40	3D-TTP: Efficient Transient Temperature-Aware Power Budgeting for 3D-Stacked Processor-Memory Systems	Sobhan Niknam, Yixian Shen, Anuj Pathania and Andy Pimentel
16:00	Compact Model Parameter Extraction using Bayesian Machine Learning	Sachin Bhat, Sourabh Kulkarni and Csaba Andras Moritz
16:20	Coffee Break
16:20	Special Session 2: Automotive	Chair: Juergen Becker (KIT, Germany)
16:40	Requirements and Applications of Cloud-based Services within the Automotive Edge	Achim Rettberg
17:10	Optimized Deployment and AI Accelerator Architectures for Autonomous Driving	Oliver Bringmann
17:40	Awards Ceremony and Closing Session
18:10	Itaipu Tour Buses depart from the lobby of the hotel at 18:10h and we arrive back to the hotel at 21:30h
21:30	Farewell Party at Hotel Cataratas

Posters
Speaker	Title
Raghava S N, Prashanth H C, Bindu G Gowda, Pratyush Nandi and Madhav Rao	Design-Space Exploration of Multiplier Approximation in CNNs
Leonardo H. Brendler, Hervé Lapuyade, Yann Deval, Ricardo Reis and François Rivet	A MCU-robust Interleaved Data/Detection SRAM for Space Environments
Harshita Gupta, Asmita Zjigyasu, Mayank Kabra and Madhav Rao	FastNTT: Design and Evaluation of Modular-Reduction based Fast NTT Design on FPGA
Marcello Munoz, Denis Maass, Murilo Perleberg, Luciano Agostini and Marcelo Porto	Efficient Hardware Design for the VVC Affine Motion Compensation Exploiting Multiple Constant Multiplication
Tiago Almeida and Lucas Wanner	Efficient Accelerator Design in High-Level Synthesis Using Approximate Logic Components
Ivan Silva and Francisco Junior	X4-RARE: Revisiting the BLIND Coarse-Grained Reconfigurable Architecture Model
Prashanth H C, Prashanth Jonna and Madhav Rao	CellFlow: Automated Standard Cell Design Flow
Ruan Formigoni, Ricardo Ferreira, Omar Paranaiba and José Augusto	L-BANCS: A Multi-Phase Tile Design for Nanomagnetic Logic
Priyanka Panigrahi and Chandan Karfa	An Investigation into the Security of Register Allocation with Spilling and Splitting
Indranee Kashyap, Dipika Deb and Nityananda Sarma	Grep: Performance Enhancement in MultiCore Processors using an Adaptive Graph Prefetcher
Trishna Rajkumar	Exploiting Routing Asymmetry for APUF Implementation in FPGA: A Proof of Concept

More details

Andre Reis (UFRGS, Brazil) - 20/7 - 14:10

Title: Embedded Tutorial - Using Virtual Boards to Teach Digital Circuit Design

Resume: The current state of the art in teaching digital design is to use an FPGA board to enable practical experiments. An alternative is to use virtual boards, that provide the FPGA board user experience based on circuit emulation. In this talk, we will demonstrate a series of experiments that are part of an introductory course starting from very simple circuits and leading to the implementation of a small microprocessor. The talk will be based on the Pitanga virtual board from inPlace Design Automation (https://en.inplace-da.com/).

Short Bio: André Reis is a Professor at the Institute of Informatics, UFRGS, Brazil, since 2000. He is a senior member of IEEE and ACM, and published more than 200 academic papers and he has also more than 10 granted USA patents. He received best paper awards from IFIP VLSI 1997, SBCCI 2013 and IWLS 2015. Andre Reis was an advisor for Nangate Inc from 2005 to 2018, and coordinated cooperation directly between UFRGS and Nangate, as well as among Nangate,UFRGS and other six european partners (Nangate, UFRGS, IMEC, Thales, ST Microelectronics, UPC, Polimi and Leading Edge) during the european FP7project Synaptic. Andre Reis is a co-founder of inPlace Design Automation, the startup offering the Pitanga platform.

Fringe Meetings: Room VIP

Tuesday 14:00: Meeting of IEEE CASS R9 Chapter Chairs
Wednesday 15:00: UNIC-CASS Committee Meeting
Thursday 15:00: ISVLSI Steering Committee Meeting

Social Event

ISVLSI Conference will provide you with an excellent experience of Brazilian fine dining, drinking and attractions.

Welcome Reception on Tuesday night by the pool of the Hotel Recanto das Cataratas

Show and Dining by the Icone Spot of the Three Frontiers where you can see the frontiers of Brazil, Argentina and Paraguay in a lovely place with restaurant, show and a beautiful view of the river Iguaçu and bridge on Wednesday evening.

Gala Dinner at the Hotel Recanto das Cataratas in a beautiful location with live music, fine dining and drinks on Thursday night.

Itaipu visit and lights, an amazing experience in the Itaipu Dam, the largest hydroelectric plant in production in the world on Friday evening.

Organization

General Chair:

Fernanda Kastensmidt, UFRGS, Brazil
Ricardo Reis, UFRGS, Brazil

Program Chairs:

Hai (Helen) Li, Duke University, USA
Aida Todri-Sanial, CNRS-LIRMM, France

Special Session Chairs:

Juergen Becker, KIT, Germany
Saraju Mohanty, University of North Texas, USA

Industry Liaison Chairs:

Victor Grimblatt, Synopsys, Chile
Linnyer Aylon, UEM, Brazil

Publication Chair:

Carolina Metzler, Cadence, Brazil

Student Research Forum Chairs

Guilherme Flach, Synopsys, USA

Publicity Chairs:

Theocharis Theocharides, Univ. Cyprus

Finance Chair:

Paulo Butzen, UFRGS, Brazil
Calebe Conceição, IFSul, Brazil

Registration Chair:

José Azambuja, UFRGS, Brazil

Submission System Chair:

Geancarlo Abich, UFRGS, Brazil

Web Chair:

Gabriel Ribeiro, IFSul, Brazil

Steering Committee:

Jürgen Becker (chair)
Saraju Mohanty (vice-chair)
Hai (Helen)Li
Lionel Torres
Michael Hübner
Nikolaos Voros
Ricardo Reis
Sandip Kundu
Sandukta Bhanja
Susmita Sur-Kolay
Theocharis Theocharides
Vijay Narayanan

Preliminary Program at a Glance

More details

Fringe Meetings: Room VIP

Social Event

Organization

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